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atmel-46003a-se-m90e32as-datasheet_052014 features metering features ? metering features fully in compliance with the requirements of iec62052-11, iec62053-22 and iec62053-23, ansi c12.1 and ansi c12.20; applicable in poly- phase class 0.2s, 0.5s or class 1 watt-hour meter or class 2 var-hour meter. ? accuracy of 0.1% for active energy and 0.2% for reactive energy over a dynamic range of 6000:1. ? temperature coefficient is 6 ppm/ (typ.) for on-chip reference voltage. automati- cally temperature compensated. ? single-point calibration on each phase over the whole dynamic range for active energy; no calibration needed for reactive/ apparent energy. ? 1 (typ.) temperatur e sensor accuracy. ? flexible piece-wise non-linearity compen sation: three current (rms value)-based segments with two programmable thresholds for each phase. independent gain and phase angle compensation for each segment. ? electrical parameters measurement: less than 0.5% fiducial error for vrms, irms, mean active/ reactive/ apparent power, frequency, power factor and phase angle. ? active (forward/reverse), reactive (forwa rd/reverse), apparent energy with indepen- dent energy registers. ? programmable startup and no-load power thresholds. ? 6 dedicated adcs for phase a/b/c current and voltage sampling circuits. current sampled over current transformer (ct) or rogowski coil (di/dt coil); voltage sam- pled over resistor divider network. ? programmable power modes: normal, idle, detection and partial measurement mode. ? fundamental (0.2%) and harmonic (1%) active energy with dedicated energy / power registers and independent energy outputs. ? current and voltage instantaneous signal monitoring. ? enhanced event detection: sag, over volt age, phase loss, over current, reverse v/i phase sequence, calculated neutral line current i nc over-current and frequency upper and lower threshold. other features ? 3.3v single power supply. operating voltage range: 2.8v~3.6v. metering accuracy guaranteed within 3.0v~3.6v. ? four-wire spi interface. ? programmable voltage sag detecti on and zero-crossing output. ? crystal oscillator frequency: 16.384mhz. on-chip two capacitors and no need of external capacitors. ? lower power consumption. i= 13ma (typ.) in normal mode. ? tqfp48 package. ? operating temperature: -40 ~ +85 . atmel m90e32as enhanced poly-phase hi gh-performance wide-span energy metering ic preliminary datasheet
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 2 application ? poly-phase energy meters of class 0.2s, 0.5s and class 1 which are used in three-phase four-wire (3p4w, y0) or three-phase three-wire (3p3w, y or ) systems. ? power monitoring instruments which need to measure voltage, current, mean power, etc. general description the m90e32as is a poly-phase high performance wide-dynamic range metering ic. the m90e32as incorporates 6 inde- pendent 2nd order sigma-delta adcs, which could be employed in three voltage channels (phase a, b and c) and three current channels (phase a, b, c) in a typical three-phase four-wire system. the m90e32as has an embedded dsp which exec utes calculation of active energy, re active energy, apparent energy, fun- damental and harmonic active energy over adc signal and on-chip reference voltage. the dsp also calculates measure- ment parameters such as voltage and current rms va lue as well as mean active/reactive/apparent power. a four-wire spi interface is provided between the m90e32as and the external microcontroller. the m90e32as is suitable for poly-phase multi-function meters which could measure active/reactive/apparent energy and fundamental/harmonic energy either through four independent energy pulse outputs cf1/cf 2/cf3/cf4 or through the cor- responding registers. the adc and auto-temperat ure compensation technology fo r reference voltage ensure the m90e32as's long-term stability over variations in grid and ambient environment conditions. block diagram figure-1 m90e32as block diagram vdd18 regulator temperature sensor current detector adc-v1 adc-v2 adc-v3 adc-i1 adc-i2 adc-i3 spi interface dsp energy metering (forward/reverse active/reactive/cf generator) measure and monitoring (v/i/rms / sag / phase / frequency) control logic zero crossing cf out power on reset crystal oscillator on-chip reference voltage vref i1p / i1n v1p / v1n cs sclk sdo sdi osci osco reset cf1 zx0 i2p / i2n i3p / i3n v2p / v2n v3p / v3n cf2 cf3 cf4 zx1 zx2 power mode configuration pm1 pm0 irq warnout irq0 irq1 warn out flexible piece-wise non-linear compensation
3 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 features .............. ................. ................ ................ .............. .............. ............... ............. ................... 1 application .............. ................ ................. .............. .............. .............. .............. ............. ................. 2 general description.......... ................ ................. ................ ................. ................ ................ ....... 2 block diagram............. ................ ................ .............. .............. ............... .............. ............ ............. 2 1 pin assignment ....... ................ ................ ................. .............. .............. .............. ............. ........... 7 2 pin description ....... ................ ................ .............. .............. ............... .............. .............. ............ 8 3 function description ........ ................ ................ ................. ................ ................. ............... .. 10 3.1 power supply ............................................................................................................... ....................................10 3.2 clock ...................................................................................................................... .............................................10 3.3 reset ...................................................................................................................... ..............................................10 3.3.1 reset pin ................................................................................................................ .................................. 10 3.3.2 power on reset (por) ..................................................................................................... ........................ 10 3.3.3 software reset ........................................................................................................... ............................... 10 3.4 analog/digital channel mapping ............................................................................................. ...............11 3.5 metering function .......................................................................................................... ...............................12 3.5.1 theory of energy registers ..................... .......................................................................... ...................... 12 3.5.2 energy registers ......................................................................................................... .............................. 13 3.5.3 energy pulse output .............................. ........................................................................ ........................... 14 3.5.4 startup and no-load power ................................................................................................ ...................... 14 3.6 measurement function ....................................................................................................... .........................16 3.6.1 active/ reactive/ apparent power ......................................................................................... .................. 16 3.6.2 fundamental / harmonic active power .......... ............................................................................ ............. 16 3.6.3 mean power factor (pf) ................................................................................................... ........................ 16 3.6.4 voltage / current rms .................................................................................................... .......................... 16 3.6.5 phase angle .............................................................................................................. ................................. 17 3.6.6 frequency ................................................................................................................ .................................. 17 3.6.7 temperature .............................................................................................................. ................................ 17 3.6.8 peak value ............................................................................................................... .................................. 17 3.7 power quality monitoring ................................................................................................... ......................18 3.7.1 instantaneous signal monitoring .......................................................................................... .................. 18 3.7.2 instantaneous signal related status and events ........................................................................... ...... 19 3.7.3 frequency monitoring related status and events ........................................................................... ..... 20 3.7.4 zero-crossing detection .......................... ........................................................................ ........................ 20 3.7.5 neutral line overcurrent de tection ....................................................................................... ................. 20 3.7.6 phase sequence error detect ion ........................................................................................... ................. 20 3.8 power mode ................................................................................................................. .....................................21 3.8.1 normal mode (n mode) ............................. ........................................................................ ........................ 21 3.8.2 idle mode (i mode) ....................................................................................................... .............................. 22 3.8.3 detection mode (d mode) .................................................................................................. ....................... 24 3.8.4 partial measurement mode (m mode) ........................................................................................ .............. 25 3.8.5 transition of power modes ................................................................................................ ...................... 26 3.9 external component compensation ............................................................................................ .........27 3.9.1 gain based compensation .................................................................................................. .................... 28 3.9.2 delay/phase based compensation ........................................................................................... .............. 29 table of contents
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 4 4 spi interface ........ ................. ................ ................ .............. ............... .............. ............ ............ 30 4.1 interface description ...................................................................................................... ...........................30 4.2 spi interface .............................................................................................................. ......................................30 4.2.1 spi slave interface format ............................................................................................... ........................ 30 4.2.2 reliability enhanc ement feature .......................................................................................... ................... 31 5 register .......... ................. ................ ................ ................. .............. .............. ............. ................ 32 5.1 register list .............................................................................................................. ......................................32 5.2 special registers .. ................. ................ ................ ................ ............. ............. ............. ................................39 5.2.1 configuration registers crc generation ........ ........................................................................... ........... 39 5.2.2 irq and warnout signal generation ............. ........................................................................... .............. 40 5.2.3 special configuration regi sters .......................................................................................... .................... 45 5.3 low-power modes registers .................................................................................................. ..................48 5.3.1 detection mode registers ................................................................................................. ....................... 48 5.3.2 partial measurement mode re gisters ....................................................................................... .............. 50 5.4 configuration and calibration registers .................................................................................... .....55 5.4.1 configuration registers .................................................................................................. ......................... 55 5.4.2 energy calibration registers ...................... ....................................................................... ...................... 57 5.4.3 fundamental/harmonic energy calibration registers ........................................................................ ... 58 5.4.4 measurement calibra tion .................................................................................................. ....................... 59 5.4.5 emm status ............................................................................................................... ................................. 59 5.5 energy register ............................................................................................................ .................................67 5.5.1 regular energy registers ................................................................................................. ....................... 67 5.5.2 fundamental / harmonic energy register ..... .............................................................................. ........... 68 5.6 measurement registers ...................................................................................................... ........................69 5.6.1 power and power factor registers ......................................................................................... ................ 69 5.6.2 fundamental/ harmonic power and voltage/ current rms registers ................................................. 70 5.6.3 peak, frequency, angle and temperature registers ......................................................................... ... 71 6 electrical specification ............ ................. ................ .............. .............. .............. ............. 7 2 6.1 electrical specification ..... ................ ................ ................ ................ ................ .............. .........................72 6.2 metering/ measurement accuracy ............................................................................................. ............74 6.2.1 metering accuracy ........................................................................................................ ............................ 74 6.2.2 measurement accura cy ..................................................................................................... ....................... 75 6.3 interface timing ........................................................................................................... ..................................76 6.3.1 spi interface timing (slave mode) ........................................................................................ .................. 76 6.4 power on reset timing ...... ................. ................ ................ ................ ................ ............... ...........................77 6.5 zero-crossing timing ....................................................................................................... .............................78 6.6 voltage sag and phase loss timing .......................................................................................... .............79 6.7 absolute maximum rating .................................................................................................... ......................80 ordering information ..... ................ ................ .............. .............. ............... .............. ............. ... 81 package dimensions ........... ................ ................. ................ ................. ................ ................ ..... 82 revision history ...... ................. ................ ................ .............. ............... .............. ............ ........... 83
5 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 table-1 pin description ...................................................................................................... .............................................. 8 table-2 power mode mapping ................................................................................................... .................................... 21 table-3 digital i/o and power pin states in idle mode ........................................................................ .......................... 22 table-4 compensation related registers ............ ........................................................................... .............................. 27 table-5 register list ........................................................................................................ .............................................. 32 table-6 configuration registers .............................................................................................. ...................................... 55 table-7 calibration registers ........................ ........................................................................ ........................................ 57 table-8 fundamental/h armonic energy calibration registers .................................................................... .................. 58 table-9 measurement calibration registers ........ ............................................................................ ............................. 59 table-10 emm status registers ................................................................................................ ...................................... 59 table-11 regular energy registers ............................................................................................ ..................................... 67 table-12 fundamental / harmonic energy register .............................................................................. .......................... 68 table-13 power and powe r factor register ..................................................................................... ............................... 69 table-14 fundamental/ harm onic power and voltage/ current rms regi sters ...................................................... ....... 70 table-15 peak, frequency, angle and temperature registers .................................................................... ................... 71 table-16 metering accuracy for di fferent energy within the dynamic range ..................................................... ............ 74 table-17 measurement pa rameter range and format .............................................................................. ..................... 75 table-18 spi timing specification ............................................................................................ ....................................... 76 table-19 power on reset specification .......... .............................................................................. .................................. 77 table-20 zero-crossing specification ......................................................................................... ..................................... 78 list of tables
6 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 figure-1 m90e32as block diagr am .............................................................................................. ................................... 2 figure-2 pin assignment (top view) .............. ............................................................................. ..................................... 7 figure-3 channel to phase m apping ............................................................................................ .................................. 11 figure-4 energy accumu lation diagram ......................................................................................... ................................ 13 figure-5 cfx pulse output regu lation ......................................................................................... .................................. 14 figure-6 active power startup/noload processing .............................................................................. ........................... 14 figure-7 fundamental active powe r startup/noload processing .................................................................. ................. 15 figure-8 harmonic active power startup/noload processing ......... ............................................................ .................... 15 figure-9 power quality monitor in datapath ............. ...................................................................... ................................ 18 figure-10 block diagram in norm al mode ....................................................................................... ................................. 21 figure-11 block diagram in idle mode ......................................................................................... ..................................... 22 figure-12 block diagram in dete ction mode .................................................................................... ................................ 24 figure-13 block diagram in partial measurement mode .......................................................................... ........................ 25 figure-14 power mode transiti on .............................................................................................. ....................................... 26 figure-15 segment gain compens ation .......................................................................................... ................................. 28 figure-16 slave mode ......................................................................................................... .............................................. 30 figure-17 read sequence ...................................................................................................... .......................................... 31 figure-18 write sequence ..................................................................................................... ........................................... 31 figure-19 crc checking diagram ............................................................................................... .................................... 39 figure-20 irq and warn out generation ......................................................................................... ................................. 40 figure-21 current detect ion register latching scheme ............ ............................................................. ......................... 48 figure-22 spi timing diagram ................................................................................................. ......................................... 76 figure-23 power on reset ti ming (m90e32as and mcu are powered on simult aneously) .......................................... 77 figure-24 power on reset timing in normal & partial measurement mode . ........................................................ ........... 77 figure-25 zero-crossing timing dia gram (per phase) ........................................................................... .......................... 78 figure-26 voltage sag and phase loss timing diagram .......................................................................... ....................... 79 list of figures
7 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 1 pin assignment figure-2 pin assignment (top view) 1 2 3 4 5 6 8 9 10 11 13 25 avdd agnd i1p i1n i2p i2n v1p v1n vref agnd warnout cs test nc ic pm0 sclk cf1 cf2 zx0 irq0 7 12 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 i3p i3n ic ic v2p v2n v3p v3n dgnd osci osco zx1 zx2 cf3 cf4 irq1 pm1 sdo sdi reset vdd18 vdd18 dgnd nc nc dgnd dvdd
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 8 2 pin description table-1 pin description name pin no. i/o type description reset 41 i lvttl reset: reset pin (active low) this pin should connect to ground through a 0.1 f filter capacitor and a 10k resistor to vdd. in application it can also directly connect to one out- put pin from microcontroller (mcu). avdd 1 i power avdd: analog power supply this pin provides power supply to the analog part. this pin should connect to dvdd and be decoupled with a 0.1 f capacitor. dvdd 48 i power dvdd: digital power supply this pin provides power supply to t he digital part. it should be decoupled with a 10 f capacitor and a 0.1 f capacitor. vdd18 42, 43 p power vdd18: digital powe r supply (1.8 v) these two pins should be connected together and connected to ground through a 10 f capacitor. dgnd 19, 44, 47 i power dgnd: digital ground agnd 2, 12 i power agnd: analog ground i1p i1n 3 4 i analog i1p: positive input for analog adc channel i1n: negative input for analog adc channel these pins are differential inputs for analog adc channel. these 6 analog adc channels can be flexibly mapped, refer to 3.4 analog/ digital channel mapping . 1 i2p i2n 5 6 i analog i2p: positive input for analog adc channel i2n: negative input for analog adc channel these pins are differential inputs for analog adc channel. these 6 analog adc channels can be flexibly mapped, refer to 3.4 analog/ digital channel mapping . 1 i3p i3n 7 8 i analog i3p: positive input for analog adc channel i3n: negative input for analog adc channel these pins are differential inputs for analog adc channel. these 6 analog adc channels can be flexibly mapped, refer to 3.4 analog/ digital channel mapping . 1 vref 11 o analog vref: output pin for reference voltage this pin should be decoupled with a 4.7 f capacitor, it is better to add a 0.1 f ceramic capacitor. v1p v1n 13 14 i analog v1p: positive input for analog adc channel v1n: negative input for analog adc channel these pins are differential inputs for analog adc channel. these 6 analog adc channels can be flexibly mapped, refer to 3.4 analog/ digital channel mapping . 1 v2p v2n 15 16 i analog v2p: positive input for analog adc channel v2n: negative input for analog adc channel these pins are differential inputs for analog adc channel. these 6 analog adc channels can be flexibly mapped, refer to 3.4 analog/ digital channel mapping . 1 v3p v3n 17 18 i analog v3p: positive input for analog adc channel v3n: negative input for analog adc channel these pins are differential inputs for analog adc channel. these 6 analog adc channels can be flexibly mapped, refer to 3.4 analog/ digital channel mapping . 1
9 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 osci 20 i osc osci: external crystal input osco: external crystal output a 16.384 mhz crystal is connected between osci and osco. there are two on-chip capacitors, therefore no need of external capacitors. osco 21 o osc zx0 zx1 zx2 22 23 24 olvttl zx2/zx1/zx0:zero-crossing output these pins are asserted when voltage or current crosses zero. zero-cross- ing mode can be configured by the zxconfig register (07h). cf1 25 o lvttl cf1: (all-phase-sum total) active energy pulse output cf2 26 o lvttl cf2: (all-phase-sum total) reactive/ apparent energy pulse output the output of this pin is dete rmined by the cf2varh bit (b7, mmode0 ). cf3 27 o lvttl cf3: (all-phase-sum total) active fundamental energy pulse output cf4 28 o lvttl cf4: (all-phase-sum total) active harmonic energy pulse output warnout 29 o lvttl warnout: fatal error warning this pin is asserted high when there is metering related parameter check- sum error. otherwise this pin stays low. refer to 5.2.2 irq and warnout signal generation . irq0 30 o lvttl irq0: interrupt output 0 this pin is asserted when one or more events in the emmintstate0 register (1cch) occur. it is deasserted when there is no bit set in the emmintstate0 register (1cch). in detection mode, the irq0 is used to indicate the outpu t of current detec- tor. the irq0 state is cleared when entering or exiting detection mode. irq1 31 o lvttl irq1: interrupt output 1 this pin is asserted when one or more events in the emmintstate1 register (1d0h) occur. it is deasserted when there is no bit set in the emmintstate1 register (1d0h). in detection mode, the irq1 is used to indicate the outpu t of current detec- tor. the irq1 state is cleared when entering or exiting detection mode. pm0 pm1 33 34 i 2 lvttl pm1/0: power mode configuration these two pins define the power mode of m90e32as. refer to ta b l e - 2 . cs 37 i 2 lvttl cs : chip select (active low) in spi mode, this pin must be driven from high to low for each read/ write operation, and maintain low for the entire operation. sclk 38 i 2 lvttl sclk: serial clock this pin is used as the clock fo r the spi interface. refer to 4 spi interface . sdo 39 o lvttl sdo: serial data output this pin is used as the data output for the spi mode. refer to 4 spi inter- face . sdi 40 i 2 lvttl sdi: serial data input this pin is used as the data input for the spi mode. refer to 4 spi interface . test 32 i lvttl this pin should be always connected to dgnd in system application. ic 9, 10, 36 lvttl these pins should be always connected to dgnd in system application. nc 35, 45, 46 nc: these pins should be left open. note 1: the channel mapping is only valid in normal mode and patial measurement mode. note 2: all the digital input pins except osci are 5 v compatible. table-1 pin description (continued) name pin no. i/o type description
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 10 3 function description 3.1 power supply the m90e32as works with single power rail 3.3v. an on-chip vo ltage regulator regulates the 1.8v voltage for the digital logic. the regulated 1.8v power is connected to the vdd18 pin. it needs to be bypassed by an external capacitor. the m90e32as has four power modes: normal (n mode), part ial measurement (m mode), detection (d mode) and idle (i mode). in idle and detection modes the 1.8v power regulator is not turned on and the digital logic is not powered. when the logic is not powered, all the configured register values ar e not kept (all context lost) ex cept for detection mode related registers (10h~13h) for detection mode configuration. the registers in partial measurement mode or normal mode have to be re-configured when transiting from idle or detec- tion mode. refer to 3.8 power mode for power mode details. 3.2 clock the m90e32as has an on-chip oscillator and ca n directly connect to an external crystal. the osci pin can also be driven with a clock source. the oscillator will be powered down in idle an d detection power modes, as described in 3.8 power mode . 3.3 reset there are three reset sources for the m90e32as: - reset pin - on-chip power on reset circuit - software reset generated by the softreset register 3.3.1 reset pin the reset pin can be asserted to reset the m90e32as. the reset pin has rc filter with typical time constant of 2 s in the i/o, as well as a 2 s (typical) de-glitch filter. any reset pulse that is shorter than 2 s can not reset the m90e32as. 3.3.2 power on reset (por) the por circuit resets the m90e32as at power up. por circuit triggers reset when: - dvdd power up with crossing the power-up threshold. refer to figure-24 . - vdd18 regulator changing from disable to enable, i.e. from idle or detection mode to partial measurement mode or normal mode. refer to figure-23 . 3.3.3 software reset chip reset can be triggered by writing to the softreset register in normal mode. the software reset is the same as the reset scope generated from the reset pin or por. these three reset sources ha ve the same reset scope. all digital logics and registers except for some special registers will be subjected to reset. ? interface logic: clock dividers ? digital core/ logic: all registers except for some special registers. refer to 5.3.1 detection mode registers .
11 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 3.4 analog/digita l channel mapping analog channel to digital channel mapping: the 6 analog adc channels can be flexibly mapped to the 6 di gital metering/measuring channels (v/i phase a/b/c). refer to the channelmapi and channelmapu registers for configuration. note that channel mapping is only valid in normal mode and patial measurement mode. figure-3 channel to phase mapping v ch_a analog digital v ch0 v ch1 v ch2 i ch0 i ch1 i ch2 v ch_b v ch_c i ch_a i ch_b i ch_c flexible channel mapping
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 12 3.5 metering function metering is enabled when any of the meteren bits are set. when metering is not enabled, the cf pulse will not be generated and ene rgy accumulator will not ac cumulate energy. all energy accumulation related status will be cleared, while start up/noload handling block relat ed status will be still working. the accumulated energy will be converted to pulse frequency on the cf pins a nd stored in the corr esponding energy reg- isters. 3.5.1 theory of energy registers the energy accumulation runs at 1 mhz clock rate by accu mulating the power value calculated by the dsp processor. the power accumulation process is equivalent to digitally integrating the instantaneous power with a delta-time of about 1us. the accumulated energy is used to calculate the cf pulses and the corresponding internal energy registers. the accumulated energy is converted to frequency of the cf pulses. one cf usually corresponds to 1kwh / mc (mc is meter constant, e.g. 3200 imp/kwh), and is usually referenced as an energy unit in this datasheet. the internal energy res- olution for accumulation and conversion is 0.01 cf. the 0.01 cf pulse energy constant is referenced as 'pl_constant'. within 0.01 cf, forward and reverse energy are counteracted . when energy exceeds 0.01 pulse, the respective forward/ reverse energy is increased. take the example of active energy. suppose: t0: forward energy register is 12.34 pulses and reverse energy register is 1.23 pulses. from t0 to t1: 0.005 forward pulses appeared. from t1 to t2: 0.004 reverse pulses appeared. from t2 to t3: 0.005 reverse pulses appeared. from t3 to t4: 0.007 reverse pulses appeared. the following table illustrates the proces s of energy accumulation process: when forward/reverse energy reaches 0.01 pulse, the respec tive register is updated. when forward or reverse energy reaches 1 pulse, cfx pins output pul se and the cfxrevst bits (b3~0, emmstate0 ) are updated. refer to figure-4 . t0 t1 t2 t3 t4 input energy + 0.005 -0.004 -0.005 -0.007 bidirectional energy accumulator 0.005 0.001 -0.004 -0.001 forward 0.01 cf 0000 reverse 0.01cf 0001 forward energy register 12.34 12.34 12.34 12.34 12.34 reverse energy register 1.23 1.23 1.23 1.23 1.24
13 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 figure-4 energy accumulation diagram for all-phase-sum total of active, reactive and (arithmetic sum) apparent energy, the associated power is obtained by sum- ming the power of the three phases. the accumulation method of all-phase-sum energy is determined by the enpc/enpb/ enpa/absenp/absenq bits (b0~b4, mmode0 ). note that the direction of a ll-phase-sum power and single-phase power might be different. 3.5.2 energy registers the m90e32as meters non-decomposed total active, reactive and apparent energy, as well as decomposed active funda- mental and harmonic energy. the registers are listed as below. 3.5.2.1 total energy registers each phase and all-phase-sum has the following registers: - active forward/ reverse - reactive forward/ reverse - apparent energy altogether there are 20 energy regist ers. those registers are defined in 5.5.1 regular energy registers . 3.5.2.2 fundamental and ha rmonic energy registers the m90e32as counts decomposed active fundamental and har monic energy. reactive energy is not decomposed to fun- damental and harmonic. the fundamental/harmonic energy is accumulated in the sa me way as active energy accumulation method described above. registers: - fundamental / harmonic - all-phase-sum / phase a / phase b / phase c - forward / reverse altogether there are 16 energy registers. refer to 5.5.2 fundamental / harmonic energy register . cf gen logic cf pulse bi-directional energy accumulator, roll over positive/ negative @ 0.01cf forward energy accumulator backward energy accumulator (-)0.01 cf (+)0.01 cf phase-a phase-b phase-c per- phase power all-phase sum power pos-cf accumulator neg-cf accumulator cf[1/2/34]revst bi-directional energy accumulator, roll over positive/ negative @ 0.01cf forward energy accumulator backward energy accumulator (-)0.01 cf (+)0.01 cf bi-directional energy accumulator, roll over positive/ negative @ 0.01cf forward energy accumulator backward energy accumulator (-)0.01 cf (+)0.01 cf bi-directional energy accumulator, roll over positive/ negative @ 0.01cf forward energy accumulator backward energy accumulator (-)0.01 cf (+)0.01 cf [p/q]ereg[a/b/c]pst [p/q]eregtpst a/b/c a/b/c total
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 14 3.5.3 energy pulse output cf1 is fixed to be total active energy output (all-phase-sum). both forward and re verse energy registers can generate the cf pulse (change of forward/ reverse direct ion can generate an interrupt if enabled). cf2 is reactive energy output (all-phase-s um) by default. it can also be configur ed to be arithmetic sum apparent energy output (all-phase-sum). cf3 is fixed to be active fundamental energy output (all-phase-sum). cf4 is fixed to be active harmonic energy output (all-phase-sum). figure-5 cfx pulse output regulation for cfx pulse width r egulation, refer to figure-5 . case1 t>=160ms, tp=80ms case 2 10ms<=t<160ms, tp=t/2 3.5.4 startup and no-load power there are startup power threshold registers (e.g. pstartth(35h)). refer to 5.4 configuration and calibration registers . the power threshold registers are defined for all-phase-sum active , reactive and apparent power. the m90e32as starts meter- ing when the corresponding all-phase-sum power is greater than the startup threshold. when the power value is lower than the startup threshold, energy is not accumulated and it is assumed as in no-load status. refer to figure-6 . there are also no-load current threshold registers for active , reactive and apparent energy metering participation for each of the 3 phases. if |p|+|q| is lowe r than the corresponding powe r threshold, that particul ar phase will not be accumu- lated. refer to the pstartth register and other threshold registers. there are also no-load status bits (the tpnoload/tqnoload bits (b14~15, fundamental / harmonic energy register )) defined to reflect the no-load status. the m90e32as does not ou tput any pulse in no-load status. the power-on state is of no-load status. figure-6 active power startup/noload processing cfx t p =80ms t p =0.5t t 160ms 10ms t<160ms phase active energy metering 0 1 0 total active energy metering abs > pstartth? 0 1 0 total active power + ena abs or arithmatic enb enc 0 1 phase active power from dsp 0 phase |p| + |q| > pphaseth? 0 1 phase active power from dsp 0 phase |p| + |q| > pphaseth? 0 1 phase active power from dsp 0 phase |p| + |q| > pphaseth? c a b active power startup/noload handling noload status
15 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 figure-7 fundamental active power startup/noload processing figure-8 harmonic active power startup/noload processing phase active fund energy metering 0 1 0 total active fund energy metering abs > pstartth? 0 1 0 total active fund power + ena abs or arithmatic enb enc 0 1 phase active power from dsp 0 phase |p| + |q| > pphaseth? 0 1 phase active power from dsp 0 phase |p| + |q| > pphaseth? 0 1 phase active fundamental power from dsp 0 phase |p| + |q| > pphaseth? c a b active power startup/noload handling noload status total active power phase active harmonic energy metering 0 1 0 total active harmonic energy metering abs > pstartth? 0 1 0 total active harmonic power + ena abs or arithmatic enb enc 0 1 phase active power from dsp 0 phase |p| + |q| > pphaseth? 0 1 phase active power from dsp 0 phase |p| + |q| > pphaseth? 0 1 phase (active total power - active fundamental power) from dsp 0 phase |p| + |q| > pphaseth? c a b active power startup/noload handling noload status total active power
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 16 3.6 measurement function measured parameters can be divided to 8 types as follows: - active/ reactive/ apparent power - fundamental/ harmonic power - rms for voltage and current - power factor - phase angle - frequency - temperature - peak value measured parameters are average values that are averaged among 16 phase-voltage cycles (about 320ms at 50hz) except for the temperature. the measured parameter update frequency is approximately 3hz. refer to table-17 . 3.6.1 active/ reactive/ apparent power active/ reactive/ apparent power measurem ent registers can be divided as below: - active, reactive, apparent power - all-phase-sum / phase a / phase b / phase c altogether there are 12 power registers. refer to 5.6.1 power and power factor registers . per-phase apparent power is defined as the produ ct of measured vrms and irms of that phase. all-phase-sum power is measured by ar ithmetically summing the per-phase measured power. the summing of phases can be configured by the mmode0 register. 3.6.2 fundamental / harmonic active power fundamental / harmonic active power measur ement registers can be divided as below: - fundamental and harmonic power - all-phase-sum / phase a / phase b / phase c altogether there are 8 power registers. refer to 5.6.2 fundamental/ harmonic power and voltage/ current rms registers . 3.6.3 mean power factor (pf) power factor is defined for those cases: a ll-phase-sum / phase a / phase b / phase c. altogether there are 4 power factor registers. refer to 5.6.1 power and power factor registers . for all-phase: for each of the phase:: 3.6.4 voltage / current rms voltage/current rms registers can be divided as follows: per-phase: phase a / phase b / phase c voltage / current neutral line current rms: neutral line current can be calculated by instantaneous value . altogether there ar e 7 rms registers. refer to 5.6.2 fundamental/ harmonic power and voltage/ current rms registers . ower apparent_p sum all_phase_ er active_pow sum all_phase_ = pf_all ower apparent_p er active_pow = pf_phase c b a n i i i i + + =
17 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 3.6.5 phase angle phase angle measurement registers can be divided as below: - phase a / phase b / phase c - voltage / current altogether there are 6 phase angle registers. refer to 5.6.3 peak, frequency, angl e and temperature registers . phase angle is measured by the time-difference betwee n the voltage and current channel of the same phase. 3.6.6 frequency the frequency is measured basing on t he zero-crossing point of voltage channels. the phase a voltage signal zero -crossing will be used to comp ute the frequency. if phase a is in the sag condition, phase c will be used. if phase c is also in sag condition, phase b will be used. if all the phases are in the sag condition, frequency will be measured based on the channel s which are not in phaseloss condition (with the same order). if all phas es are lost, the fre quency will return zero. the frequency data is not averaged (updated cycle by cycle). refer to 5.6.3 peak, frequency, angle and temperature registers . 3.6.7 temperature chip junction-temperature is measured roughly every 100 ms by on-chip temperature sensor. refer to 5.6.3 peak, frequency, angle and temperature registers . 3.6.8 peak value altogether there are 6 peak value registers. refer to 5.6.3 peak, frequency, angl e and temperature registers . refer to 3.7.1 instantaneous signal monitoring .
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 18 3.7 power quality monitoring figure-9 power quality monitor in datapath 3.7.1 instantaneous signal monitoring peak detection function: peak value for each channel was detected within timing period configured by the p eakdet_period bits (b15~8, sagpeak- detcfg ). the detected peak value is updated on period intersection. registers: the peak value detected can be accessed thro ugh register u/i peak registers. refer to 5.6.3 peak, frequency, angle and temperature registers . pga adc + offset peak detector sag detector phaseloss detector ov detector phase angle phase sequence, frequency + offset oi detector peak detector zx v-channel i-channel phase -a phase -b phase -c frequency range map pga adc dsp freq based comp 50/60 zx map
19 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 3.7.2 instantaneous signal related status and events the registers involved are ovth , oith , sagth , phaselossth and sagpeakdetcfg . the result can be reflected in emmstate0 and emmstate1 registers, as well as emmintstate0 and emmintstate1 registers if the corresponding bits in emminten0 / emminten1 registers are set. the threshold value has the following relationship with the rms register (msb-16bit): here vigain is ugain register value or igain register value. 3.7.2.1 sag detection usually in the application the sag threshold is set to be 78 % of the reference voltage. the m90e32as generates sag event when there are less than three 8khz samples (absolute value) greater than the sag threshold in one detecting period. refer to 6.6 voltage sag and phase loss timing . the detecting period length can be configured by the sag_period bits (b7~0, sagpeakdetcfg ). sag status is asserted when there is no voltage instantaneo us sample's absolute value goes beyond the sag threshold in any phase. sag status is cleared when there are three samples detected with absolute va lue above the sag threshold. for the computation of sag threshold register value, refer to application note 46103. the sag event is captured by the sagphaseintst bits (b14-12, emmintstate1 ). if the corresponding irq enable bits the sagphaseinten bits (b14-12, emminten1 ) is set, irq can be generated. refer to figure-26 . 3.7.2.2 phase loss detection the phase loss detection detects if there is one or more ph ases? voltage is less than the phase-loss threshold voltage. the processing and handling is similar to sag detection, only the threshold is different. the threshold computation flow is also similar. the typical threshold setting could be 10% un or less. if any phase line is detected as in phase-loss mode, that phase?s zero-crossing detection function (both voltage and cur- rent) is disabled. 3.7.2.3 over voltage (ov) detection when any phase's absolute voltage sample instantaneous value goes beyond the over voltage threshold, the over voltage status is asserted. the status is de-asserted when the volt age sample instantaneous value go back below the over voltage threshold. change of the over voltage status can generate interrupt and flagged in the emmstate0 and emmintstate0 registers. 3.7.2.4 over current (oi) detection when any phase's absolute current sample instantaneous value go beyond the over current threshold, the over current status is asserted. the status is de-asserted when the curren t sample instantaneous value go back below the over current threshold. change of the over current status can generate interrupt and flagged in the emmstate0 and emmintstate0 registers. 2 vigain 2 e rmsregvalu = ue xxthregval 14 ?
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 20 3.7.3 frequency monitoring related status and events the measured frequency is compared with two thresholds configured in the the freqloth register and the freqhith regis- ter. if the measured frequency goes beyond the range defined by the two thresholds, the freqlost bit (b11, emmstate1 ) and freqhist bit (b15, emmstate1 ) will be asserted. the interrupt status will be updated as well; and if enabled, interrupt signal can be asserted. 3.7.4 zero-crossing detection zero-crossing detector detects the zero-cro ssing point of the fundamental component of voltage and current for each of the 3 phases. refer to 6.5 zero-crossing timing . zero-crossing signal can be independently confi gured and output. refer to the definition of the zxconfig register. 3.7.5 neutral line overcurrent detection the neutral line rms current (calculated) i nc is checked with the threshold defined in the inwarnth register. if the n line current is greater than the th reshold, the inov0st bit (b7, emmstate0 ) is set. irq0 is generated if the inov0inten bit (b7, emminten0 ) is set. 3.7.6 phase sequence error detection the phase sequence is detected in two cases: 3p4w and 3p3w, which is defined by the 3p3w bit (b8, mmode0 ). 3p4w case: correct sequence: voltage/current zero-cross ing sequence: phase-a, phase-b and phase-c. 3p3w case: correct sequence: voltage/current zero-crossing between phase-a and phase-c is greater than 180 degree. if the above mentioned criteria are vi olated, it is assumed as a phase se quence error, the urevwnst bit (b9, emmstate0 ) or the irevwnst bit (b9, emmstate0 ) will be set.
21 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 3.8 power mode the m90e32as has four power modes. the power mo de is solely defined by the pm1 and pm0 pins. 3.8.1 normal mode (n mode) in normal mode, the default is that all function blocks are active except for current detector block. refer to figure-10 . the current detector can be enabled and calibrated in normal mode using control bits in detectctrl register. figure-10 block diagram in normal mode table-2 power mode mapping pm1:pm0 value power mode 11 normal (n mode) 10 partial measurement (m mode) 01 detection (d mode) 00 idle (i mode) vdd18 regulator temperature sensor current detector adc-v1 adc-v2 adc-v3 adc-i1 adc-i2 adc-i3 spi interface dsp energy metering (forward/reverse active/reactive/cf generator) measure and monitoring (v/i/rms / sag / phase / frequency) control logic zero crossing cf out power on reset crystal oscillator on-chip reference voltage vref i1p / i1n v1p / v1n cs sclk sdo sdi osci osco reset cf1 zx0 i2p / i2n i3p / i3n v2p / v2n v3p / v3n cf2 cf3 cf4 zx1 zx2 power mode configuration pm1 pm0 irq warnout irq0 irq1 warn out flexible piece-wise non-linear compensation disabled
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 22 3.8.2 idle mode (i mode) in idle mode, all functions are shut off. the analog blocks' power supply is powered but circuits are se t into power-down mode, i.e, power supply applied but all current paths are shut off. there is very low current sinc e only very low device leakage could exist in this mode. the digital i/os' supply is powered. in i/o and analog interfac e, the input signals from digital core (which is not powered) will be set to known state as described in ta b l e - 3 . the pm1 and pm0 pins which are controlled by external mcu are active and can configure the m90e32as to other modes. figure-11 block diagram in idle mode please note that since the digital i/o is not shut off, the i/o circuit is active in the idle mode. the application shall make sure that valid logic levels are applied to the i/o. ta b l e - 3 lists digital i/o and power pins? states in idle mode. it lis ts the requirements for inputs and the output level for out- put. table-3 digital i/o and power pin states in idle mode name i/o type type pin state in idle mode reset i lvttl input level shall be vdd33. cs ilvttl i/o set in input mode. input level shall be vdd33 or vss. sclk i lvttl i/o set in input mode. input level shall be vdd33 or vss. sdo o lvttl i/o set in input mode. input level shall be vdd33 or vss. sdi i lvttl i/o set in input mode. input level shall be vdd33 or vss. pm1 pm0 ilvttl as defined in table-2 . vdd18 regulator temperature sensor current detector adc-v1 adc-v2 adc-v3 adc-i1 adc-i2 adc-i3 spi interface dsp energy metering (forward/reverse active/reactive/cf generator) measure and monitoring (v/i/rms / sag / phase / frequency) control logic zero crossing cf out power on reset crystal oscillator on-chip reference voltage vref i1p / i1n v1p / v1n cs sclk sdo sdi osci osco reset cf1 zx0 i2p / i2n i3p / i3n v2p / v2n v3p / v3n cf2 cf3 cf4 zx1 zx2 power mode configuration pm1 pm0 irq warnout irq0 irq1 warn out flexible piece-wise non-linear compensation disabled
23 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 osci osco i o osc oscillator powered down. osco stays at fixed (low) level. zx0 zx1 zx2 olvttl0 cf1 cf2 cf3 cf4 olvttl0 warnout o lvttl 0 irq0 irq1 olvttl0 vdd18 i power regulated 1.8v: high impedance dvdd i power digital power supply: powered by system avdd i power analog power supply: powered by system test i input always tie to gr ound in system application table-3 digital i/o and power pin states in idle mode (continued) name i/o type type pin state in idle mode
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 24 3.8.3 detection mode (d mode) in detection mode, the current detector is active. the curr ent detector compares whether any phase current exceeds the configured threshold using low-power comparators. when the current of one phase or multiple phases exceeds the configured threshold, the m90e32as asserts the irq0 pin to high and hold it until power mode change. the irq0 state is cleared when entering or exiting detection mode. when the current of all three current channels exceed the configured threshold, the m90e32as asserts the irq1 pin to high and hold it until power mode change. the irq1 st ate is cleared when entering or exiting detection mode. the threshold registers need to be programmed in normal mode before entering detection mode. the digital i/o state is the same as that in idle state (except for irq0/irq1 and pm1/pm0). the m90e32as has two comparators for detecting each phase?s positive and negative current. each comparator?s thresh- old can be set individually. the two comparators are both acti ve by default, which called ?double-side detection?. user also can enable one comparator only to save power co nsumption, which called ?s ingle-side detection?. double-side detection has faster response and can detect ?hal f-wave? current. but it consumes nearly twice as much power as single-side detection. comparators can be power-down by configuring the detectctrl register. the current detector can be enabled and calibrated in normal mode using control bits in the detectctrl register. figure-12 block diagram in detection mode vdd18 regulator temperature sensor current detector adc-v1 adc-v2 adc-v3 adc-i1 adc-i2 adc-i3 spi interface dsp energy metering (forward/reverse active/reactive/cf generator) measure and monitoring (v/i/rms / sag / phase / frequency) control logic zero crossing cf out power on reset crystal oscillator on-chip reference voltage vref i1p / i1n v1p / v1n cs sclk sdo sdi osci osco reset cf1 zx0 i2p / i2n i3p / i3n v2p / v2n v3p / v3n cf2 cf3 cf4 zx1 zx2 power mode configuration pm1 pm0 irq warnout irq0 irq1 warn out flexible piece-wise non-linear compensation disabled
25 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 3.8.4 partial measurement mode (m mode) in this mode, all the measurements are through the same hardware that does the measurement in the normal mode. to save power, the energy accumu lation block and a portion of the dsp computat ion code will not be ru nning in this mode. in this mode, there are configuration bits in the pmpwrctrl register to get lower power if the application allows: ? option to turn-off the three analog voltage channel if there is no need to measure voltage and power. ? option to lower down the digital clock from 16.384mhz to 8.192mhz in partial measurement mode, c rc checking will be disabled. the interrupts will not be generated. figure-13 block diagram in partial measurement mode vdd18 regulator temperature sensor current detector adc-v1 adc-v2 adc-v3 adc-i1 adc-i2 adc-i3 spi interface dsp energy metering (forward/reverse active/reactive/cf generator) measure and monitoring (v/i/rms / sag / phase / frequency) control logic zero crossing cf out power on reset crystal oscillator on-chip reference voltage vref i1p / i1n v1p / v1n cs sclk sdo sdi osci osco reset cf1 zx0 i2p / i2n i3p / i3n v2p / v2n v3p / v3n cf2 cf3 cf4 zx1 zx2 power mode configuration pm1 pm0 irq warnout irq0 irq1 warn out flexible piece-wise non-linear compensation disabled
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 26 3.8.5 transition of power modes the above power modes are controlled by the pm0 and pm1 pins . in application, the pm0 and pm1 pins are connected to external mcu. the pm0 and pm1 pins have internal rc- filters. generally, the m90e32as stays in idle mode most of the time while outage. it enters detection mode at a certain interval (for example 5s) as controlled by the mcu. it informs the mc u if the current exceeds the configured threshold. the mcu then commands the m90e32as to enter partial measurement mode at a certain interval (e.g. 60s) to read related current. after current reading, the m90e32as gets back to the idle mode. the measured current may be used to count energy according to some metering model (lik e current rms multiplying the rated voltage to compute the power). any power mode transition goes through the idle mode, as shown in figure-14 . figure-14 power mode transition normal mode idle mode detection mode partial measurement mode
27 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 3.9 external component compensation the calibrated channel gain and phase-delay offset could be tuned with respect to some reference parameter. this feature is useful when external component is not ideal and allow low cost sensors used in the system. there are three reference parameters: ? measured current rms (per phase) ? measured line frequency (all phase in common) ? measured temperature there are two tuning parameters to compensate: ? channel gain compensation ? channel phase delay compensation following are the compensation correspondences: ? measured current rms is per phase. it goes to igain and phi for each phase. ? this is to compensate the non-linearity of current sensor s, like a current-transformer. non-linearity can be gain-non- linearity or phase nonlinearity. the gain nonlinearity is compensated by igain compensation and phase nonlinearity is compensated by phase compensation. ? frequency compensation only goes to phi/delay (all phases are the same). ? temperature compensation only goes to ugain (per phase). table-4 compensation related registers parameter describtion registers logirms measured current rms logirms0 , logirms1 f0 nominal line frequency f0 t0 nominal temperature t0 gainirms gain comp ensation for irms gainairms01 , gainairms2, gainbirms01, gainbirms2, gaincirms01, gaincirms2 phiirms phase compen sation for irms phiairms01 , phiairms2, phibirms01, phibirms2, phicirms01, phicirms2 ugaint temperature compensation only goes to ugain ugaintab , ugaintc phif frequency compensation only goes to phi/delay phifreqcomp
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 28 3.9.1 gain based compensation the channel gain can be tuned automatically according to measured temperature and current rms. here log(x) = log 2 (x)*16, e.g.: log(2) = 16, log(16) = 64 ? gain0 is the calibrated gain at nominal condition, ? gainirms is the gain adjustment per irms change (8 bit) ? irms_ref is the reference current rms ? gainirms_offset is the offset for segment calibration ? ugain0 is the calibrated gain at nominal temperature ? ugaint is the gain adjustment per temperature degree change, ? t0 is the nominal temperature, if (irms > irms0) gainirms = gainirms0, irms_ref = irms0, gainirms_offset = 0, if (irms1 29 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 3.9.2 delay/phase based compensation the channel phase compensation delay can be tuned according to the measured frequency and current rms. ? phi0 is the calibrated delay between the v/i channel (in terms of 2.048mhz clock cycles) ? phif is the delay change per frequency change ? f0 is the nominal frequency, ? phiirms is the delay change per current change ? phi_offset is the offset for segment calibration ? log(x)= log 2 (x)*16 if (irms > irms0) phiirms = phiirms0, irms_ref = irms0, phi_offset=0 if (irms1 m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 30 4 spi interface 4.1 interface description four pins are associated with the interface as below: ? sdi ? data pin, input. ? sdo ? data pin, output. ? sclk ? clock input pin. ? cs ? chip select pin input. figure-16 slave mode 4.2 spi interface the interface works in slave mode as shown in figure-16 . 4.2.1 spi slave interface format in the spi mode, data on sdi is shifted into the chip on the rising edge of sclk while data on sdo is shifted out of the chip on the falling edge of sclk. refer to figure-17 and figure-18 below for the timing diagram. access type: the first bit on sdi defines the access type as below: address: fixed 15-bit, following the access type bits. the lower 10-bit is decoded as address; the higher 5 bits are ?don't care?. read/write data: fixed as 16 bits. read sequence: instruction description instruction format read read from registers 1 write write to registers 0 spi interface logic (as slave) miso mosi sck cs host controller in master mode sck gpio1 mosi miso sclk cs sdi sdo
31 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 figure-17 read sequence write sequence: figure-18 write sequence 4.2.2 reliability enhancement feature the spi read/write transaction is cs -low defined. each transaction can only access one register. within each cs -low defined transaction: write: access occurs only when cs goes from low to high and there ar e exactly 32 sclk cycles received during cs low period. read: if sclk>=16 (full address received), data is read out from internal registers and gets to the sdo pin; and the lasts- pidata register is updated. the r/c regi sters can only be cleared after the lastspidata register is updated. cs sclk sdi sdo 10 1 2 3 4 5 6 7 8 9 111213141516171819202122 24 a3 a6 a5 a4 register address high impedance d15 don't care d0 16-bit data 23 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 25 26 a2 a1 a0 27 28 29 30 31 32 a8 x x x x x a7 a9 cs sclk sdi sdo 10 123456789 11121314151617181920212223 a3 a7 a6 a5 a4 16-bit data high impedance d0 d7 d6 d5 d4 d3 d2 d1 register address d15 24 d14d13d12d11d10 d9 d8 a0 a1 a2 25 26 27 28 29 30 31 32 a8 x x x x x a9
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 32 5register 5.1 register list table-5 register list register address register name read/ write type functional description comment page status and special register 00h meteren r/w metering enable p41 01h channelmapi r/w current channel mapping configuration p42 02h channelmapu r/w voltage channel mapping configuration p42 05h sagpeakdetcfg r/w sag and peak detector period configuration p44 06h ovth r/w over voltage threshold p44 07h zxconfig r/w zero-crossing configuration configuration of zx0/1/2 pins? source p45 08h sagth r/w voltage sag threshold p45 09h phaselossth r/w voltage phase losing threshold similar to voltage sag threshold register p45 0ah inwarnth r/w neutral current (calcula ted) warning thresh- old p46 0bh oith r/w over current threshold p46 0ch freqloth r/w low threshold for frequency detection p46 0dh freqhith r/w high threshold for frequency detection p46 0eh pmpwrctrl r/w partial measurement mode power control p47 0fh irq0mergecfg r/w irq0 merge configuration refer to 4.2.2 reliability e nhancement feature p47 low power mode register 10h detectctrl r/w current detect control p48 11h detectth1 r/w channel 1 current threshold in detection mode p49 12h detectth2 r/w channel 2 current threshold in detection mode p49 13h detectth3 r/w channel 3 current threshold in detection mode p49 14h idcoffseta r/w phase a current dc offset p50 15h idcoffsetb r/w phase b current dc offset p50 16h idcoffsetc r/w phase c current dc offset p50 17h udcoffseta r/w voltage dc offset for channel a p50 18h udcoffsetb r/w voltage dc offset for channel b p50 19h udcoffsetc r/w voltage dc offset for channel c p51 1ah ugaintab r/w voltage gain temperature compensation for phase a/b p51 1bh ugaintc r/w voltage gain temperature compensation for phase c p51 1ch phifreqcomp r/w phase compensation for frequency p51 20h logirms0 r/w current (log irms0) configuration for seg- ment compensation p51 21h logirms1 r/w current (log irms1) configuration for seg- ment compensation p51
33 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 22h f0 r/w nominal frequency p52 23h t0 r/w nominal temperature p52 24h phiairms01 r/w phase a phase compensation for current segment 0 and 1 p52 25h phiairms2 r/w phase a phase compensation for current segment 2 p52 26h gainairms01 r/w phase a gain compensation for current seg- ment 0 and 1 p53 27h gainairms2 r/w phase a gain compensation for current seg- ment 2 p53 28h phibirms01 r/w phase b phase compensation for current segment 0 and 1 p53 29h phibirms2 r/w phase b phase compensation for current segment 2 p54 2ah gainbirms01 r/w phase b gain compensation for current seg- ment 0 and 1 p53 2bh gainbirms2 r/w phase b gain compensation for current seg- ment 2 p54 2ch phicirms01 r/w phase c phase compensation for current segment 0 and 1 p54 2dh phicirms2 r/w phase c phase compensation for current segment 2 p54 2eh gaincirms01 r/w phase c gain compensation for current seg- ment 0 and 1 p54 2fh gaincirms2 r/w phase c gain compensation for current seg- ment 2 p54 configuration registers 31h plconsth r/w high word of pl_constant refer to table-6 . p55 32h plconstl r/w low word of pl_constant p56 33h mmode0 r/w metering method configuration p56 34h mmode1 r/w pga gain configuration p57 35h pstartth r/w active startup power threshold 36h qstartth r/w reactive startup power threshold 37h sstartth r/w apparent startup power threshold 38h pphaseth r/w startup power threshold for any phase (active energy accumulation) 39h qphaseth r/w startup power threshold for any phase (reactive energy accumulation) 3ah sphaseth r/w startup power threshold for any phase (apparent energy accumulation) table-5 register list (continued) register address register name read/ write type functional description comment page
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 34 calibration registers 41h poffseta r/w phase a active power offset refer to table-7 . p57 42h qoffseta r/w phase a reactive power offset p58 43h poffsetb r/w phase b active power offset 44h qoffsetb r/w phase b reactive power offset 45h poffsetc r/w phase c active power offset 46h qoffsetc r/w phase c reactive power offset 47h pqgaina r/w phase a calibration gain p58 48h phia r/w phase a calibration phase angle p58 49h pqgainb r/w phase b calibration gain 4ah phib r/w phase b calibration phase angle 4bh pqgainc r/w phase c calibration gain 4ch phic r/w phase c calibration phase angle fundamental/ harmonic energy calibration registers 51h poffsetaf r/w phase a fundamental active power offset refer to table-8 . 52h poffsetbf r/w phase b fundamental active power offset 53h poffsetcf r/w phase c fundamental active power offset 54h pgainaf r/w phase a fundamental calibration gain 55h pgainbf r/w phase b fundamental calibration gain 56h pgaincf r/w phase c fundamental calibration gain measurement calibration registers 61h ugaina r/w phase a voltage rms gain refer to table-9 . 62h igaina r/w phase a current rms gain 63h uoffseta r/w phase a voltage rms offset 64h ioffseta r/w phase a current rms offset 65h ugainb r/w phase b voltage rms gain 66h igainb r/w phase b current rms gain 67h uoffsetb r/w phase b voltage rms offset 68h ioffsetb r/w phase b current rms offset 69h ugainc r/w phase c voltage rms gain 6ah igainc r/w phase c current rms gain 6bh uoffsetc r/w phase c voltage rms offset 6ch ioffsetc r/w phase c current rms offset table-5 register list (continued) register address register name read/ write type functional description comment page
35 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 emm status registers 70h softreset r/w software reset p59 71h emmstate0 r emm state 0 p60 72h emmstate1 r emm state 1 p61 73h emmintstate0 r/w1c emm interrupt status 0 p62 74h emmintstate1 r/w1c emm interrupt status 1 p63 75h emminten0 r/w emm interrupt enable 0 p64 76h emminten1 r/w emm interrupt enable 1 p65 78h lastspidata r last read/write spi value p65 79h crcerrstatus r crc error status p66 7ah crcdigest r/w crc digest p66 7fh cfgregaccen r/w configure register access enable p66 energy register 80h apenergyt r/c total forward active energy refer to table-11 . p67 81h apenergya r/c phase a forward active energy 82h apenergyb r/c phase b forward active energy 83h apenergyc r/c phase c forward active energy 84h anenergyt r/c total reverse active energy 85h anenergya r/c phase a reverse active energy 86h anenergyb r/c phase b reverse active energy 87h anenergyc r/c phase c reverse active energy 88h rpenergyt r/c total forward reactive energy 89h rpenergya r/c phase a forward reactive energy 8ah rpenergyb r/c phase b forward reactive energy 8bh rpenergyc r/c phase c forward reactive energy 8ch rnenergyt r/c total reverse reactive energy 8dh rnenergya r/c phase a reverse reactive energy 8eh rnenergyb r/c phase b reverse reactive energy 8fh rnenergyc r/c phase c reverse reactive energy 90h saenergyt r/c total (arithmetic sum) apparent energy 91h senergya r/c phase a apparent energy 92h senergyb r/c phase b apparent energy 93h senergyc r/c phase c apparent energy table-5 register list (continued) register address register name read/ write type functional description comment page
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 36 fundamental / harmonic energy register a0h apenergytf r/c total forward active fundamental energy refer to table-12 . p68 a1h apenergyaf r/c phase a forward active fundamental energy a2h apenergybf r/c phase b forward active fundamental energy a3h apenergycf r/c phase c forward active fundamental energy a4h anenergytf r/c total reverse active fundamental energy a5h anenergyaf r/c phase a reverse active fundamental energy a6h anenergybf r/c phase b reverse active fundamental energy a7h anenergycf r/c phase c reverse active fundamental energy a8h apenergyth r/c total forward active harmonic energy a9h apenergyah r/c phase a forward active harmonic energy aah apenergybh r/c phase b forward active harmonic energy abh apenergych r/c phase c forward active harmonic energy ach anenergyth r/c total reverse active harmonic energy adh anenergyah r/c phase a reverse active harmonic energy aeh anenergybh r/c phase b reverse active harmonic energy afh anenergych r/c phase c reverse active harmonic energy table-5 register list (continued) register address register name read/ write type functional description comment page
37 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 power and power factor registers b0h pmeant r total (all-phase-sum) active power refer to table-13 . p69 b1h pmeana r phase a active power b2h pmeanb r phase b active power b3h pmeanc r phase c active power b4h qmeant r total (all-phase-sum) reactive power b5h qmeana r phase a reactive power b6h qmeanb r phase b reactive power b7h qmeanc r phase c reactive power b8h smeant r total (arithmetic sum) apparent power b9h smeana r phase a apparent power bah smeanb r phase b apparent power bbh smeanc r phase c apparent power bch pfmeant r total power factor bdh pfmeana r phase a power factor beh pfmeanb r phase b power factor bfh pfmeanc r phase c power factor c0h pmeantlsb r lower word of total (all-phase-sum) active power c1h pmeanalsb r lower word of phase a active power c2h pmeanblsb r lower word of phase b active power c3h pmeanclsb r lower word of phase c active power c4h qmeantlsb r lower word of total (all-phase-sum) reactive power c5h qmeanalsb r lower word of phase a reactive power c6h qmeanblsb r lower word of phase b reactive power c7h qmeanclsb r lower word of phase c reactive power c8h sameantlsb r lower word of total (arithmetic sum) appar- ent power c9h smeanalsb r lower word of phase a apparent power cah smeanblsb r lower word of phase b apparent power cbh smeanclsb r lower word of phase c apparent power fundamental / harmonic power and voltage / current rms registers d0h pmeantf r total active fundamental power refer to table-14 . p70 d1h pmeanaf r phase a active fundamental power d2h pmeanbf r phase b active fundamental power d3h pmeancf r phase c active fundamental power d4h pmeanth r total active harmonic power d5h pmeanah r phase a active harmonic power d6h pmeanbh r phase b active harmonic power d7h pmeanch r phase c active harmonic power d9h urmsa r phase a voltage rms dah urmsb r phase b voltage rms dbh urmsc r phase c voltage rms table-5 register list (continued) register address register name read/ write type functional description comment page
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 38 dch irmsn r n line calculated current rms ddh irmsa r phase a current rms deh irmsb r phase b current rms dfh irmsc r phase c current rms e0h pmeantflsb r lower word of total active fundamental power e1h pmeanaflsb r lower word of phase a active fundamental power e2h pmeanbflsb r lower word of phase b active fundamental power e3h pmeancflsb r lower word of phase c active fundamental power e4h pmeanthlsb r lower word of total active harmonic power e5h pmeanahlsb r lower word of phase a active harmonic power e6h pmeanbhlsb r lower word of phase b active harmonic power e7h pmeanchlsb r lower word of phase c active harmonic power e9h urmsalsb r lower word of phase a voltage rms eah urmsblsb r lower word of phase b voltage rms ebh urmsclsb r lower word of phase c voltage rms edh irmsalsb r lower word of phase a current rms eeh irmsblsb r lower word of phase b current rms efh irmsclsb r lower word of phase c current rms peak, frequency, angle and temperature registers f1h upeaka r channel a voltage peak refer to table-15 . p71 f2h upeakb r channel b voltage peak p71 f3h upeakc r channel c voltage peak f5h ipeaka r channel a current peak f6h ipeakb r channel b current peak f7h ipeakc r channel c current peak f8h freq r frequency f9h panglea r phase a mean phase angle fah pangleb r phase b mean phase angle fbh panglec r phase c mean phase angle fch temp r measured temperature fdh uanglea r phase a voltage phase angle feh uangleb r phase b voltage phase angle ffh uanglec r phase c voltage phase angle table-5 register list (continued) register address register name read/ write type functional description comment page
39 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 5.2 special registers 5.2.1 configuration registers crc generation the registers between address ?0h? to ?6fh? are considered as user configuration registers. crc-16 with the following polynomial was used to compute the crc digest: the crc computation rate is every 16 bit word per 125us. the result can be read from the crc result register. the device can automatically monitor the crc changes versus a golden crc which is latched after the first time the crc computation is done. the latching event is tr iggered by none "0x55aa" value written to the cfgregaccen register (which means configuration done) , followed by a new crc result available even t. once golden crc is latched, the crc_cmp signal is enabled. subsequent crc result will be compared with the la tched crc to generate t he crc error status. crc error status can be read, and if configured, can goes to warn or irq0 pins to alert the mcu in the case of crc error. figure-19 crc checking diagram 1 + x + x + x = polynomial 5 12 16 00h 01h 02h 03h ... 6ch 6dh 6eh 6fh crc digest (computed) crc engine error crc err crc digest (golden) compare user read and crc_cmp regaccen != 0x55aa? y
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 40 5.2.2 irq and warnout signal generation the interrupt generation scheme is consistent for all the inte rrupt sources. for any interrupt source, there is an interrupt status register and an interrupt enable register. interrupt stat us register latches the interrup t event and is always available for polling. if the interr upt enable register is set, that interrupt can go to irq pin to notify the processor. the interrupt status register is write-1-to-clear. it captures the interrupt event which is usually an internal state change. t he (real time) internal state for that event is also available for read at any time. the following diagram illustrates how the status bits, enable bits and irq/ warnout pins work together. figure-20 irq and warnout generation there are two interrupt output pins: irq0 and irq1. the irq 0 is associated with interrupt sources defined in emmstate0 register. the irq 1 is associated with interrupt sources defined in emmstate1 register. if configured, irq 1 state can be ored together with irq0 stat e and output to irq0, in that case mcu need only process one irq pin. it is up to system designer to trade off betwee n conveniences of locating interrupt source and saving gpio pins. the warn pin will be asserted w hen there is a configuration register crc ch eck error. the warn si gnal can be merged to irq0 if configured. irq0/1 warnout state reg change event gen int status reg and int en reg state reg change event gen int status reg and int en reg state reg change event gen int status reg and int en reg status reg change event gen int status reg and int en reg state 1 state 2 state 3 status 4 internal err cfgcrc err and warnirqen reg
41 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 meteren metering enable address: 00h type: read/write default value: 00h bit name description 7:0 meteren[7:0] metering is enabled when any bit in this re gister is set.
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 42 channelmapi current channel mapping configuration address: 01h type: read/write default value: 0210h bit name description 15:11 - reserved. 10:8 ic_src adc input source for phase c current channel 7- reserved. 6:4 ib_src adc input source for phase b current channel 3- reserved. 2:0 ia_src adc input source for phase a current channel code adc input source 000 i0 001 i1 010 i2 011 fixed-0 100 u0 101 u1 110 u2 111 fixed-0 code adc input source 000 i0 001 i1 010 i2 011 fixed-0 100 u0 101 u1 110 u2 111 fixed-0 code adc input source 000 i0 001 i1 010 i2 011 fixed-0 100 u0 101 u1 110 u2 111 fixed-0
43 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 channelmapu voltage channel mapping configuration address: 02h type: read/write default value: 0654h bit name description 15:11 - reserved. 10:8 uc_src adc input source for phase c voltage channel 7- reserved. 6:4 ub_src adc input source for phase b voltage channel 3- reserved. 2:0 ua_src adc input source for phase a voltage channel code adc input source 000 i0 001 i1 010 i2 011 fixed-0 100 u0 101 u1 110 u2 111 fixed-0 code adc input source 000 i0 001 i1 010 i2 011 fixed-0 100 u0 101 u1 110 u2 111 fixed-0 code adc input source 000 i0 001 i1 010 i2 011 fixed-0 100 u0 101 u1 110 u2 111 fixed-0
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 44 sagpeakdetcfg sag and peak detector period configuration ovth over voltage threshold address: 05h type: read/write default value: 143fh bit name description 15:8 peakdet_peri od period in which the peak detector detects the u/i peak. unit is ms. 7:0 sag_period period in which the phase voltage needs to stay below the sagth before to assert the sag status. unit is ms. the phase loss detector also uses this parameter in detecting phase loss. address: 06h type: read/write default value: c000h bit name description 15:0 ovth over voltage threshold. 0xffff maps to adc output full-scale peak.
45 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 5.2.3 special config uration registers zxconfig zero-crossing configuration sagth voltage sag threshold phaselossth voltage phase losing threshold address: 07h type: read/write default value: 0001h bit name description 15:13 zx2src[2:0] these bits select the signal source for the zx2, zx1 or zx0 pins. 12:10 zx1src[2:0] 9:7 zx0src[2:0] 6:5 zx2con[1:0] these bits configure zero-c rossing type for the zx2, zx1 and zx0 pins. 4:3 zx1con[1:0] 2:1 zx0con[1:0] 0zxdis this bit determines whether to disable the zx signals: 0: enable 1: disable all the zx signals to ?0? (default). address: 08h type: read/write default value: 1000h bit name description 15:0 sagth voltage sag threshold level. 0xffff map to adc output full-scale peak. address: 09h type: read/write default value: 0400h bit name description 15:0 phaselossth phaseloss threshold level 0xffff map to adc output full-scale peak. code source 011 fixed-0 000 ua 001 ub 010 uc 111 fixed-0 100 ia 101 ib 110 ic code zero-crossing configuration 00 positive zero-crossing 01 negative zero-crossing 10 all zero-crossing 11 no zero-cro ssing output
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 46 inwarnth neutral current (calculated) warning threshold oith over current threshold freqloth low threshold for frequency detection freqhith high threshold for frequency detection address: 0ah type: read/write default value: ffffh bit name description 15:0 inwarnth0 neutral current (calculated) warning threshold. threshold for calculated (ia + ib +ic) n line rms current. unsigned 16 bit, unit 1ma. if n line rms current is greater than the threshold, the inov0st bit (b7, emmstate0 ) bit is asserted if enabled. refer to 3.7.5 neutral line overcurrent detection . address: 0bh type: read/write default value: c000h bit name description 15:0 oith over current threshold. 0xffff maps to adc output full-scale peak. address: 0ch type: read/write default value: 1324h bit name description 15:0 freqloth low threshold for frequency detection. address: 0dh type: read/write default value: 13ech bit name description 15:0 freqhith high threshold for frequency detection.
47 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 pmpwrctrl partial measurement mode power control irq0mergecfg irq0 merge configuration address: 0eh type: read/write default value: 010fh bit name description 15:9 - reserved. 8 pmpwrdown- vch in partial measurement mode the v0/v1/v2 analog channel can be powered off to save power 0: power on 1: power off this feature can be used when voltage meas urement is not required in partial mode. 3 actrl_clk_ gate power off the clock of analog control block to save power. 0: power on 1: power off 2 dsp_clk_g ate power off the clock of dsp register to save power. 0: power on 1: power off 1 mtms_clk_ gate power off the metering and measuring block to save power. 0: power on 1: power off 0 pmclklow in partial measurement mode the main clock can be reduced to 8.192mhz to save power. 0: 16.384mhz 1: 8.192mhz in this low rate mode, the spi interface only support half the access rate at normal mode. address: 0fh type: read/write default value: 0000h bit name description 15:2 - reserved. 1 warn_or the warn state can be ored to irq0 output 0: normal 1: ored 0irq1_or the irq1 state can be ored to irq0 output 0: normal 1: ored
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 48 5.3 low-power modes registers 5.3.1 detection mode registers current detection register latching scheme is: when any of the 4 current detection registers (0x10 - 0x13) we re programmed, all the 4 current detection registers (includ- ing the registers that no t being programmed) will be automatically latched into the curren t detector's internal configuration latches at the same time. those latched configur ation values are not subject to digita l reset signals and will be kept in all the 4 power modes. the power up value of those latches is not deterministic, so user needs to program the current detec- tion registers to update. figure-21 current detection register latching scheme detectctrl current detect control address: 10h type: read/write default value: xxxxh bit name description 15:7 - must be written ?3?. 6 detcalen detector calibration in normal mode is enabled if this bit is set. the default written value is ?0?. if set, current detectors are enabled and irq0/1 are assigned to current detector outputs as if in detect mode. the current detector can be calibrated. 5:0 detectctrl detector power-down, active high: [5:3]: power-down for negative detector of channel 3/2/1; [2:0]: power-down for positi ve detector of channel 3/2/1. the default written value is ?0?. 0x10 0x11 0x12 0x13 latch latch latch latch current detector register write update registers current detector block
49 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 detectth1 channel 1 current threshold in detection mode detectth2 channel 2 current threshold in detection mode detectth3 channel 3 current threshold in detection mode address: 11h type: read/write default value: 0000h bit name description 15:8 calcoden channel 1 current negative detector calculation code. code mapping: 8'b0000-0000, vc = -1.2mv = --0.85mvrms (vc is the threshold of low power computation) 8'b1111-1111, vc = 9mv = 6.35mvrms dac typical resolution is [9- (-1.2)]/256 = 40 v = 28 vrms 7:0 calcodep channel 1 current positive detector calculation code. code mapping: 8'b0000-0000, vc = -1.2mv = --0.85mvrms (vc is the threshold of low power computation) 8'b1111-1111, vc = 9mv = 6.35mvrms dac typical resolution is [9- (-1.2)]/256 = 40 v = 28 vrms address: 12h type: read/write default value: 0000h bit name description 15:8 calcoden channel 2 current negative detector calculation code. code mapping: 8'b0000-0000, vc = -1.2mv = --0.85mvrms (vc is the threshold of low power computation) 8'b1111-1111, vc = 9mv = 6.35mvrms dac typical resolution is [9- (-1.2)]/256 = 40 v = 28 vrms 7:0 calcodep channel 2 current positive detector calculation code. code mapping: 8'b0000-0000, vc = -1.2mv = --0.85mvrms (vc is the threshold of low power computation) 8'b1111-1111, vc = 9mv = 6.35mvrms dac typical resolution is [9- (-1.2)]/256 = 40 v = 28 vrms address: 13h type: read/write default value: 0000h bit name description 15:8 calcoden channel 3 current negative detector calculation code. code mapping: 8'b0000-0000, vc = -1.2mv = --0.85mvrms (vc is the threshold of low power computation) 8'b1111-1111, vc = 9mv = 6.35mvrms dac typical resolution is [9- (-1.2)]/256 = 40 v = 28 vrms 7:0 calcodep channel 3 current positive detector calculation code. 8'b0000-0000, vc = -1.2mv = --0.85mvrms (vc is the threshold of low power computation) 8'b1111-1111, vc = 9mv = 6.35mvrms dac typical resolution is [9- (-1.2)]/256 = 40 v = 28 vrms
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 50 5.3.2 partial measurement mode registers idcoffseta phase a current dc offset idcoffsetb phase b current dc offset idcoffsetc phase c current dc offset udcoffseta voltage dc offset for channel a udcoffsetb voltage dc offset for channel b address: 14h type: read/write default value: 0000h bit name description 15:0 idcoffseta phase a current dc offset in decimator, signed with complement format. address: 15h type: read/write default value: 0000h bit name description 15:0 idcoffsetb phase b current dc offset in decimator, signed with complement format. address: 16h type: read/write default value: 0000h bit name description 15:0 idcoffsetc phase c current dc offset in decimator, signed with complement format. address: 17h type: read/write default value: 0000h bit name description 15:0 udcoffseta phase a voltage dc offset in decimator, signed with complement format. address: 18h type: read/write default value: 0000h bit name description 15:0 udcoffsetb phase b voltage dc offset in decimator, signed with complement format.
51 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 udcoffsetc voltage dc offset for channel c ugaintab voltage gain temperature compensation for phase a/b ugaintc voltage gain temperature compensation for phase c phifreqcomp phase compensation for frequency logirms0 current (log irms0) configuration for segment compensation address: 19h type: read/write default value: 0000h bit name description 15:0 udcoffsetc phase c voltage dc offset in decimator, signed with complement format. address: 1ah type: read/write default value: 0000h bit name description 15:8 ugaintb voltage gain temperature compensation for phase b. 7:0 ugainta voltage gain temperature compensation for phase a. address:1bh type: read/write default value: 0000h bit name description 15:8 - reserved. 7:0 ugaintc voltage gain temperature compensation for phase c. address: 1ch type: read/write default value: 0000h bit name description 15:8 - reserved. 7:0 phif phase compensation for frequency. address: 20h type: read/write default value: 0000h bit name description 15:8 - reserved. 7:0 logirms0 = log2(irms0), irms0 is th e nominal rms current at calibration.
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 52 logirms1 current (log irms1) configuration for segment compensation f0 nominal frequency t0 nominal temperature phiairms01 phase a phase compensation for current segment 0 and 1 phiairms2 phase a phase compensation for current segment 2 address: 21h type: read/write default value: 0000h bit name description 15:8 - reserved. 7:0 logirms1 = log2(irms1), irms1 is th e nominal rms current at calibration. address: 22h type: read/write default value: 5000 bit name description 15:0 f0 nominal frequency. for example, 5000 corresponds to 50.00hz. address: 23h type: read/write default value: 25 bit name description 15:8 - reserved. 7:0 t0 signed, nominal temperature in degree c. address: 24h type: read/write default value: 0000h bit name description 15:8 phiirms1 phase compensation for current segment 1(irms1 irms0). refer to 3.9.2 delay/phase based compen- sation. address: 25h type: read/write default value: 0000h bit name description 15:8 - reserved. 7:0 phiirms2 phase compensation for current se gment 2 (irms < irms1). refer to 3.9.2 delay/phase based compen- sation.
53 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 gainairms01 phase a gain compensation for current segment 0 and 1 gainairms2 phase a gain compensation for current segment 2 phibirms01 phase b phase compensation for current segment 0 and 1 phibirms2 phase b phase compensation for current segment 2 gainbirms01 phase b gain compensation for current segment 0 and 1 address: 26h type: read/write default value: 0000h bit name description 15:8 gainirms1 gain compensation for current segmen t 1 (irms1 irms0). refer to 3.9.1 gain based compensation. address: 27h type: read/write default value: 0000h bit name description 15:8 - reserved. 7:0 gainirms2 gain compensati on for current segment 2 (irms < irms1). refer to 3.9.1 gain based compensation. address: 28h type: read/write default value: 0000h bit name description 15:8 phiirms1 phase compensation for current segment 1 (irms1 irms0). refer to 3.9.2 delay/phase based compen- sation. address: 29h type: read/write default value: 0000h bit name description 15:8 - reserved. 7:0 phiirms2 phase compensation for current se gment 2 (irms < irms1). refer to 3.9.2 delay/phase based compen- sation. address: 2ah type: read/write default value: 0000h bit name description 15:8 gainirms1 gain compensation for current segmen t 1 (irms1 irms0). refer to 3.9.1 gain based compensation.
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 54 gainbirms2 phase b gain compensation for current segment 2 phicirms01 phase c phase compensation for current segment 0 and 1 phicirms2 phase c phase compensation for current segment 2 gaincirms01 phase c gain compensation for current segment 0 and 1 gaincirms2 phase c gain compensation for current segment 2 address: 2bh type: read/write default value: 0000h bit name description 15:8 - reserved. 7:0 gainirms2 gain compensati on for current segment 2 (irms < irms1). refer to 3.9.1 gain based compensation. address: 2ch type: read/write default value: 0000h bit name description 15:8 phiirms1 phase compensation for current segment 1 (irms1 irms0). refer to 3.9.2 delay/phase based compen- sation. address: 2dh type: read/write default value: 0000h bit name description 15:8 - reserved. 7:0 phiirms2 phase compensation for current se gment 2 (irms < irms1). refer to 3.9.2 delay/phase based compen- sation. address: 2eh type: read/write default value: 0000h bit name description 15:8 gainirms1 gain compensation for current segmen t 1 (irms1 irms0). refer to 3.9.1 gain based compensation. address: 2fh type: read/write default value: 0000h bit name description 15:8 - reserved. 7:0 gainirms2 gain compensati on for current segment 2 (irms < irms1). refer to 3.9.1 gain based compensation.
55 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 5.4 configuration and ca libration registers 5.4.1 configuration registers plconsth high word of pl_constant table-6 configuration registers register address register name read/write type functional description power-on value and comments configuration registers 31h plconsth r/w high word of pl_constant 0861h 32h plconstl r/w low word of pl_constant c468h 33h mmode0 r/w hpf/integrator on/off, cf and all-phase energy computation configuration 0087h 34h mmode1 r/w pga gain configuration 0000h 35h pstartth r/w active st artup power threshold. 0000h. 16 bit unsigned integer, unit: 0.00032 watt 36h qstartth r/w reactive startup power threshold. 0000h 16 bit unsigned integer, unit: 0.00032 var 37h sstartth r/w apparent startup power threshold. 0000h 16 bit unsigned integer, unit: 0.00032 va 38h pphaseth r/w startup power threshold (for |p|+|q| of a phase) for any phase participating active e nergy accumulation. common for phase a/ b/c. 0000h 16 bit unsigned integer, unit: 0.00032 watt/var 39h qphaseth r/w startup power threshold (for |p|+|q| of a phase) for any phase participating reac- tive energy accumulation. common for phase a/b/c. 0000h 16bit unsigned integer, unit: 0.00032 watt/var 3ah sphaseth rw startup power threshold (for |p|+|q| of a phase) for any phase participating appar- ent energy accumulation. common for phase a/b/c. 0000h 16 bit unsigned integer, unit: 0.00032 watt/var address: 31h type: read/write default value: 0861h bit name description 15:0 plcon- sth[15:0] the plconsth[15:0] and plconstl[15:0] bits are high word and low word of pl_constant respectively. pl_constant is a constant which is proportional to the sampling ratios of voltage and current, and inversely proportional to the meter constant. pl_const ant is a threshold for energy calculated inside the chip, i.e., energy larger than pl_constant will be accumulated as 0.01cfx in the corresponding energy registers and then output on cfx if one cf reaches. it is suggested to set pl_constant as a multiple of 4 so as to double or redouble meter constant in low current state to save verifi cation time.
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 56 plconstl low word of pl_constant mmode0 metering method configuration address: 32h type: read/write default value: c468h bit name description 15:0 plcon- stl[15:0] the plconsth[15:0] and plconstl[15:0] bits are high word and low word of pl_constant respectively. it is suggested to set pl_constant as a multiple of 4. address: 33h type: read/write default value: 0087h bit name description 15-13 - reserved. 12 freq60hz current grid operating line frequency. 0: 50hz (default) 1: 60hz 11 hpfoff disable hpf in the signal processing path. 10 didten enable integrator for didt current sensor. 0: disable (default) 1: enable 9 - reserved. 83p3w this bit defines the voltage/curr ent phase sequence detection mode: 0: 3p4w (default) 1: 3p3w (ua is uab, uc is ucb, ub is not used) 7cf2varh cf2 pin source: 0: apparent energy 1: reactive energy (default) 6-5 - reserved. 4 absenq these bits configure the calculation method of tota l (all-phase-sum) reactive/active energy and power: 0: arithmetic sum: (default) et=ea*enpa+ eb*enpb+ ec*enpc pt= pa*enpa+ pb*enpb+ pc*enpc 1: absolute sum: et=|ea|*enpa+ |eb|*enpb+ |ec|*enpc pt=|pa|*enpa+ |pb|*enpb+ |pc|*enpc note: et is the total (all-phase-sum) energy, ea/eb /ec are the signed phase a/b/c energy respectively. reverse energy is negative. pt is the total (all-ph ase-sum) power, pa/pb/pc are the signed phase a/b/c power respectively. reverse power is negative. 3 absenp 2enpa these bits configure whether phase a/b/c are co unted into the all-phase sum energy/power (p/q/s). 1: corresponding phase a/b/c to be counted into the all-phase sum energy/power (p/q/s) (default) 0: corresponding phase a/b/c not counted into the all-phase sum energy/power (p/q/s) 1enpb 0enpc
57 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 mmode1 pga gain configuration 5.4.2 energy calibration registers poffseta phase a active power offset address: 34h type: read/write default value: 0000h bit name description 15-6 - reserved. 5-0 pga_gain pga gain for all adc channels. mapping: [5:4]: i3 [3:2]: i2 [1:0]: i1 encoding: 00: 1x (default) 01: 2x 10: 4x 11: n/a table-7 calibration registers register address register name read/write type functional description power-on value calibration registers 41h poffseta r/w phase a active power offset 0000h 42h qoffseta r/w phase a reactive power offset 0000h 43h poffsetb r/w phase b active power offset 0000h 44h qoffsetb r/w phase b reactive power offset 0000h 45h poffsetc r/w phase c active power offset 0000h 46h qoffsetc r/w phase c reactive power offset 0000h 47h pqgaina r/w phase a active/reactive energy cali- bration gain 0000h 48h phia r/w phase a calibration phase angle 0000h 49h pqgainb r/w phase b active/reactive energy cali- bration gain 0000h 4ah phib r/w phase b calibration phase angle 0000h 4bh pqgainc r/w phase c active/reactive energy cali- bration gain 0000h 4ch phic r/w phase c calibration phase angle 0000h address: 41h type: read/write default value: 0000h bit name description 15-0 offset phase a active power offset, signed with complement format.
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 58 qoffseta phase a reactive power offset pqgaina phase a active/reactive energy calibration gain phia phase a calibration phase angle 5.4.3 fundamental/harmonic en ergy calibration registers address: 42h type: read/write default value: 0000h bit name description 15-0 offset phase a reactive power offset, signed with complement format. address: 47h type: read/write default value: 0000h bit name description 15-0 gain phase a energy gain, signed with complement format. address: 48h type: read/write default value: 0000h bit name description 15 delayv 0: delay cycles are applied to current channel. (default) 1: delay cycles are applied to voltage channel. 14:8 - reserved. 7:0 delaycycles number of delay cycles calculated in phase compensation. unit is 2.048mhz cycle. it is an unsigned 8 bit integer. table-8 fundamental/harmonic energy calibration registers register address register name read/write type functional description power-on value 51h poffsetaf r/w phase a fundamental active power offset 0000h 52h poffsetbf r/w phase b fundamental active power offset 0000h 53h poffsetcf r/w phase c fundamental active power offset 0000h 54h pgainaf r/w phase a fundamental calibration gain 0000h 55h pgainbf r/w phase b fundamental calibration gain 0000h 56h pgaincf r/w phase c fundamental calibration gain 0000h
59 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 5.4.4 measureme nt calibration 5.4.5 emm status softreset software reset table-9 measurement calibration registers register address register name read/write type functional description power-on value 61h ugaina r/w phase a voltage rms gain 8000h 62h igaina r/w phase a current rms gain 8000h 63h uoffseta r/w phase a voltage rms offset 0000h 64h ioffseta r/w phase a current rms offset 0000h 65h ugainb r/w phase b voltage rms gain 8000h 66h igainb r/w phase b current rms gain 8000h 67h uoffsetb r/w phase b voltage rms offset 0000h 68h ioffsetb r/w phase b current rms offset 0000h 69h ugainc r/w phase c voltage rms gain 8000h 6ah igainc r/w phase c current rms gain 8000h 6bh uoffsetc r/w phase c voltage rms offset 0000h 6ch ioffsetc r/w phase c current rms offset 0000h table-10 emm status registers register address register name read/write type functional description power-on value 70h softreset w software reset 71h emmstate0 r emm state 0 72h emmstate1 r emm state 1 73h emmintstate0 r/w1c emm interrupt status 0 74h emmintstate1 r/w1c emm interrupt status 1 75h emminten0 r/w emm interrupt enable 0 76h emminten1 r/w emm interrupt enable 1 78h lastspidata r/w1c last read/write spi value 79h crcerrstatus r crc error status 7ah crcdigest r/w crc digest 7fh cfgregaccen r/w configure register access enable address: 70h type: write default value: 0000h bit name description 15:0 softre- set[15:0] software reset register. the m90e32as resets if 789ah is written to this register. the reset domain is the same as the reset pin or power on reset. reading th is register always return 0.
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 60 emmstate0 emm state 0 address: 71h type: read default value: 0000h bit name description 15 oiphaseast set to 1: if there is over current on phase a 14 oiphasebst set to 1: if there is over current on phase b 13 oiphasecst set to 1: if there is over current on phase c 12 ovphaseast set to 1: if there is over voltage on phase a 11 ovphasebst set to 1: if there is over voltage on phase b 10 ovphasecst set to 1: if there is over voltage on phase c 9 urevwnst voltage phase sequence error status 8irevwnst current phase sequence error status 7inov0st when the calculated n line current is greater than the threshold set by the inwarnth register, this bit is set. 6 tqnoloadst all phase sum reactive power no-load condition status 5 tpnoloadst all phase sum active power no-load condition status 4 tasnoloadst all phase arithmetic sum appare nt power no-load condition status 3cf1revst energy for cf1 forward/reverse status: 0: forward 1: reverse 2cf2revst energy for cf2 forward/reverse status: 0: forward 1: reverse 1cf3revst energy for cf3 forward/reverse status: 0: forward 1: reverse 0cf4revst energy for cf4 forward/reverse status: 0: forward 1: reverse
61 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 emmstate1 emm state 1 address: 72h type: read default value: 0000h bit name description 15 freqhist this bit indicates whether frequency is greater than the high threshold 14 sagphase- ast this bit indicates whether there is voltage sag on phase a 13 sag- phasebst this bit indicates whether there is voltage sag on phase b 12 sagpha- secst this bit indicates whether there is voltage sag on phase c 11 freqlost this bit indicates whether frequency is lesser than the low threshold 10 phaselos- sast this bit indicates whether there is a phase loss in phase a 9 phaseloss- bst this bit indicates whether there is a phase loss in phase b 8 phaseloss- cst this bit indicates whether there is a phase loss in phase c 7 qeregtpst reactive (q) energy (e) register (reg) of all channel total sum (t) positive (p) status (st): 0: positive, 1: negative 6 qeregapst reactive (q) energy (e) register (reg) of channel (a/b/c) positi ve (p) status (st): 0: positive, 1: negative 5 qeregbpst 4 qeregcpst 3 peregtpst active (p) energy (e) register (reg) of all channel total sum (t) positive (p) status (st) 0: positive, 1: negative 2 peregapst active (p) energy (e) register (reg) of channel (a/b/c) positive (p) status (st) 0: positive, 1: negative 1 peregbpst 0 peregcpst
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 62 emmintstate0 emm interrupt status 0 address: 73h type: read/ write 1 clear default value: 0000h bit name description 15 oiphaseaints t over current on phase a status change flag 14 oiphasebints t over current on phase b status change flag 13 oiphasecint st over current on phase c status change flag 12 ovphaseaint st over voltage on phase a status change flag 11 ovphasebint st over voltage on phase b status change flag 10 ovphasecint st over voltage on phase c status change flag 9 urevwn- intst voltage phase sequence error status change flag 8 irevwnintst current phase sequence error status change flag 7 inov0intst neutral line over current status change flag 6 tqnoload- intst all phase sum reactive power no-load condition status change flag 5 tpnoload- intst all phase sum active power no-load condition status change flag 4 tasnoload- intst all phase arithmetic sum apparent powe r no-load condition status change flag 3cf1revintst energy for cf1 forward/reverse status change flag 2cf2revintst energy for cf2 forward/reverse status change flag 1cf3revintst energy for cf3 forward/reverse status change flag 0cf4revintst energy for cf4 forward/reverse status change flag
63 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 emmintstate1 emm interrupt status 1 address: 74h type: read/ write 1 clear default value: 0000h bit name description 15 freqhiintst freqhist change flag 14 sagphase- aintst voltage sag on phase a status change flag 13 sagphase- bintst voltage sag on phase b status change flag 12 sagphase- cintst voltage sag on phase c status change flag 11 freqlointst freqlost change flag 10 phaselos- saintst voltage phaseloss on phase a status change flag 9 phaseloss- bintst voltage phaseloss on phase b status change flag 8 phaseloss- cintst voltage phaseloss on phase c status change flag 7 qeregt- pintst reactive (q) energy (e) register (reg) of all channel total sum (t) positive (p) status change flag (intst) 6 qeregap- intst reactive (q) energy (e) register (reg) of all cha nnel (a/b/c) positive (p) status change flag (intst) 5 qeregb- pintst 4 qe regcpintst 3 peregt- pintst active (p) energy (e) register (reg) of all channel total sum (t) positive (p) status change flag (intst) 2 peregap- intst active (p) energy(e) register (reg) of channel (a/b/c) positive (p) status change flag (intst) 1 peregb- pintst 0 pe regcpintst
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 64 emminten0 emm interrupt enable 0 address: 75h type: read/ write default value: 0000h bit name description 15 oiphaseainte n phase a over current status change interrupt generation enable 14 oiphasebinte n phase b over current status change interrupt generation enable 13 oiphasecint en phase c over current status change interrupt generation enable 12 ovphaseaint en phase a over voltage status change interrupt generation enable 11 ovphasebint en phase b over voltage status change interrupt generation enable 10 ovphasecint en phase c over voltage status change interrupt generation enable 9 urevwninte n voltage phase sequence error status change interrupt generation enable 8 irevwninten current phase sequence error status change interrupt generation enable 7 inov0inten neutral line over current status change interrupt generation enable 6 tqnoloadinte n all phase sum reactive power no-load conditi on status change interrupt generation enable 5 tpnoloadinte n all phase sum active power no-load condition status change interrupt generation enable 4 tasnoload- inten all phase arithmetic sum apparent power no-load c ondition status change interrupt generation enable 3cf1revinten energy for cf1 forward/reverse status change interrupt generation enable 2cf2revinten energy for cf2 forward/reverse status change interrupt generation enable 1cf3revinten energy for cf3 forward/reverse status change interrupt generation enable 0cf4revinten energy for cf4 forward/reverse status change interrupt generation enable
65 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 emminten1 emm interrupt enable 1 lastspidata last read/write spi value address: 76h type: read/ write default value: 0000h bit name description 15 freqhiinten freqhiintst status change interrupt generation enable 14 sagphase- ainten phase a sag status change interrupt generation enable 13 sagphase- binten phase b sag status change interrupt generation enable 12 sagphase- cinten phase c sag status change interrupt generation enable 11 freqlointen freqlointst status change interrupt generation enable 10 phaselos- sainten phase a phase loss status change interrupt generation enable 9 phaseloss- binten phase b phase loss status change interrupt generation enable 8 phaseloss- cinten phase c phase loss status change interrupt generation enable 7 qeregtpinte n reactive (q) energy(e) register (reg) of all channel totoal sum (t) positive (p) status change interrupt generation enable (inten) 6 qeregap- inten 5 qeregb- pinten 4 qe regcpinten 3 peregtpinte n active (p) energy (e) register (reg) of channel a (a ) positive (p) status change interrupt generation e nable (st) 2 peregapinte n 1 peregbpinte n 0 peregcpinte n address: 78h type: read default value: 0000h bit name description 15:0 lastspi- data[15:0] this register is a special register which logs data of the previous spi read or write access especially for read/clear registers. this register is useful when the user wants to ch eck the integrity of the last spi access.
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 66 crcerrstatus crc error status crcdigest crc digest cfgregaccen configure register access enable address: 79h type: read default value: 0000h bit name description 15:2 - reserved. 1 int_err internal register crc error 0 cfg_crc_e rr configuration registers crc error address: 7ah type: read/ write default value: 0000h bit name description 15:0 crcdigest this register returns the computed crc remainder (diges t) value of the public co nfiguration register upon read operation. this register can be conditionally written as the portal to update the golden crc that internally latched. refer to register cfgregaccen for the details. address: 7fh type: read/ write default value: 0000h bit name description 15:0 cfgregaccen enable register access configuration. ?0x55aa? : allow register configurat ion access (configuration operation). ?0xaa55?: allow write to the "golden crc" register at the address of crcdigest, on top of normal operation/crc checking mode. this is just for validation of this feature. other: normal operation. the devic e will start to compute a crc diges t/checksum and latch it the golden crc register, then continuously running to check with it.
67 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 5.5 energy register 5.5.1 regular energy registers table-11 regular energy registers register address register name read/write type functional description comment 80h apenergyt r/c total forward active energy resolution is 0.01cf. cleared after read. 81h apenergya r/c phase a forward active energy 82h apenergyb r/c phase b forward active energy 83h apenergyc r/c phase c forward active energy 84h anenergyt r/c total reverse active energy 85h anenergya r/c phase a reverse active energy 86h anenergyb r/c phase b reverse active energy 87h anenergyc r/c phase c reverse active energy 88h rpenergyt r/c total forward reactive energy 89h rpenergya r/c phase a forward reactive energy 8ah rpenergyb r/c phase b forward reactive energy 8bh rpenergyc r/c phase c forward reactive energy 8ch rnenergyt r/c total reverse reactive energy 8dh rnenergya r/c phase a reverse reactive energy 8eh rnenergyb r/c phase b reverse reactive energy 8fh rnenergyc r/c phase c reverse reactive energy 90h saenergyt r/c total (arithmetic sum) apparent e nergy 91h senergya r/c phase a apparent energy 92h senergyb r/c phase b apparent energy 93h senergyc r/c phase c apparent energy
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 68 5.5.2 fundamental / harmonic energy register table-12 fundamental / harmonic energy register register address register name read/write type functional description comment a0h apenergytf r/c total forward active fundamental e nergy resolution is 0.01cf. cleared after read. a1h apenergyaf r/c phase a forward active fundamental energy a2h apenergybf r/c phase b forward active fundamental energy a3h apenergycf r/c phase c forward active fundamen- tal energy a4h anenergytf r/c total reverse active fundamental e nergy a5h anenergyaf r/c phase a reverse active fundamen- tal energy a6h anenergybf r/c phase b reverse active fundamen- tal energy a7h anenergycf r/c phase c reverse active fundamental energy a8h apenergyth r/c total forward active harmonic energy a9h apenergyah r/c phase a forward active harmonic e nergy aah apenergybh r/c phase b forward active harmonic e nergy abh apenergych r/c phase c forward active harmonic e nergy ach anenergyth r/c total reverse active harmonic energy adh anenergyah r/c phase a reverse active harmonic e nergy aeh anenergybh r/c phase b reverse active harmonic e nergy afh anenergych r/c phase c reverse active harmonic e nergy
69 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 5.6 measurement registers 5.6.1 power and power factor registers table-13 power and power factor register register address register name read/write type functional description comment b0h pmeant r total (all-phase-sum) active power complement, power=32-bit register value* 0.00032 w b1h pmeana r phase a active power b2h pmeanb r phase b active power b3h pmeanc r phase c active power b4h qmeant r total (all-phase-sum) reactive power complement, power=32-bit register value* 0.00032 var b5h qmeana r phase a reactive power b6h qmeanb r phase b reactive power b7h qmeanc r phase c reactive power b8h sameant r total (arithmetic sum) apparent power complement, power=32-bit register value* 0.00032 va b9h smeana r phase a apparent power bah smeanb r phase b apparent power bbh smeanc r phase c apparent power bch pfmeant r total power factor signed with complement format, x.xxx lsb is 0.001. range from -1000 to +1000 bdh pfmeana r phase a power factor beh pfmeanb r phase b power factor bfh pfmeanc r phase c power factor c0h pmeantlsb r lower word of total (all-phase-sum) active power lower word of active powers. c1h pmeanalsb r lower word of phase a active power lower word of active powers. c2h pmeanblsb r lower word of phase b active power c3h pmeanclsb r lower word of phase c active power c4h qmeantlsb r lower word of total (all-phase-sum) reactive power lower word of reactive powers. c5h qmeanalsb r lower word of phase a reactive power lower word of reactive powers. c6h qmeanblsb r lower word of phase b reactive power c7h qmeanclsb r lower word of phase c reactive power c8h sameantlsb r lower word of total (arithmetic sum) apparent power lower word of apparent powers. c9h smeanalsb r lower word of phase a apparent power lower word of apparent powers. cah smeanblsb r lower word of phase b apparent power cbh smeanclsb r lower word of phase c apparent power note: the power regisiters are all of 32-bit. the c0h~cb h registers are the lower words of the b0h~bfh registers.
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 70 5.6.2 fundamental/ harmonic power and voltage/ current rms registers table-14 fundamental/ harmonic power and voltage/ current rms registers register address register name read/write type functional description comment d0h pmeantf r total active fundamental power complement, power=32-bit register value* 0.00032 w d1h pmeanaf r phase a active fundamental power complement, power=32-bit register value* 0.00032 w d2h pmeanbf r phase b active fundamental power d3h pmeancf r phase c active fundamental power d4h pmeanth r total active harmonic power complement, power=32-bit register value* 0.00032 w d5h pmeanah r phase a ac tive harmonic power complement, power=32-bit register value* 0.00032 w d6h pmeanbh r phase b ac tive harmonic power d7h pmeanch r phase c active harmonic power d9h urmsa r phase a voltage rms unsigned, 1lsb corresponds to 0.01 v dah urmsb r phase b voltage rms dbh urmsc r phase c voltage rms dch irmsn r n line calculated current rms unsigned 16-bit integer with unit of 0.001a 1lsb corresponds to 0.001 a ddh irmsa r phase a current rms deh irmsb r phase b current rms dfh irmsc r phase c current rms e0h pmeantflsb r lower word of total active funda- mental power lower word of d0h register. e1h pmeanaflsb r lower word of phase a active funda- mental power lower word of registers from d1h to d3h. e2h pmeanbflsb r lower word of phase b active funda- mental power e3h pmeancflsb r lower word of phase c active funda- mental power e9h urmsalsb r lower word of phase a voltage rms lower word of registers from d9h to dbh. eah urmsblsb r lower word of phase b voltage rms ebh urmsclsb r lower word of phase c voltage rms edh irmsalsb r lower word of phase a current rms lower word of registers from ddh to dfh. eeh irmsblsb r lower word of phase b current rms efh irmsclsb r lower word of phase c current rms note: the power regisiters are all of 32-bit. the e0h~ef h registers are the lower words of the d0h~dfh registers.
71 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 5.6.3 peak, frequency, angl e and temperature registers upeaka channel a voltage peak ipeaka channel a current peak table-15 peak, frequency, angle and temperature registers register address register name read/write type functional description comment f1h upeaka r channel a voltage peak f2h upeakb r channel b voltage peak f3h upeakc r channel c voltage peak f5h ipeaka r channel a current peak f6h ipeakb r channel b current peak f7h ipeakc r channel c current peak f8h freq r frequency 1lsb corresponds to 0.01 hz f9h panglea r phase a mean phase angle unsigned, 1lsb corresponds to 0.1 degree, 0~+360.0 fah pangleb r phase b mean phase angle fbh panglec r phase c mean phase angle fch temp r measured temperature 1lsb corresponds to 1 c signed, msb as the sign bit fdh uanglea r phase a voltage phase angle always ?0? feh uangleb r phase b voltage phase angle unsigned, 1lsb corresponds to 0.1 degree, 0~+360.0 ffh uanglec r phase c voltage phase angle address: f1h type: read default value: 0000h bit name description 15:0 upeakdataa channel a voltage peak data detected in the configured period. component. unit is v. upeak is calculated as below: here ugainregvalue is the register valu e of the ugain (61h/65h/69h) register. address: f5h type: read default value: 0000h bit name description 15:0 ipeakdataa channel a current peak data det ected in the configured period. component. unit is a. ipeak is calculated as below: here igainregvalue is the register value of the igain (62h/66h/6ah) register. 13 2 100 lue ugainregva lue upeakregva = upeak 13 2 1000 lue igainregva lue ipeakregva = ipeak
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 72 6 electrical specification 6.1 electrical specification parameter min typ max unit test condition/ comments accuracy dc power supply rejection ratio (psrr) 0.1 % vdd=3.3v 0.3v, i=5a, v=220v, ct 1000:1, sampling resistor 4.8 ac power supply rejection ratio (psrr) 0.1 % vdd=3.3v superimposes 400mvrms, i=5a, v=220v, ct 1000:1, sampling resistor 4.8 active energy error (dynamic range 6000:1) 0.1 % ct 1000:1, sampling resistor 4.8 adc channel channel differential input 120 720m vrms pga=1 note1 voltage channel input impedance 120 k pga=1 current channel input impedance 120 80 50 k pga=1 pga=2 pga=4 channel sampling frequency 8 khz channel sampling bandwidth 2 khz temperature sensor and reference temperature sensor accuracy 1c reference voltage 1.2 v 3.3 v, 25 c reference voltage temperature coefficient 615 ppm/ c from -40 to 85 c current detectors current detector threshold range 1.5 4 mvrms 3.3 v, 25 c current detector threshold setting step/ resolu- tion 0.05 mvrms 3.3 v, 25 c current detector detection time (single-side) 32 ms current detector detection time (double-side) 17 ms crystal oscillator oscillator frequency ( f sys_clk ) 16.384 mhz the accuracy of crystal or external clock is 20 ppm, 10pf ~ 20pf crystal load capacitor integrated. power supply avdd 2.8 3.3 3.6 v dvdd 2.8 3.3 3.6 v vdd18 1.8 v operating currents normal mode operating current (i-normal) 13 ma 3.3 v, 25 c idle mode operating current (i-idle) <0.1 1 a detection mode operating current (i-detection) 200 100 230 115 a double-side detection single-side detection partial measurement m ode operating current (i-measurement) 7ma 3.3 v, 25c
73 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 spi slave mode (spi) bit rate 400 1100k note bps esd charged device model (cdm) 500 v jesd22-c101 human body model (hbm) 2000 v jesd22-a114 latch up 100 ma jesd78a latch up 5.4 v jesd78a dc characteristics digital input high level (all digital pins except osci) 2.0 5.5 v vdd=3.3v, 5v digital input compatible digital input low level (all digital pins except osci) 0.8 v vdd=3.3v digital input leakage current 1 a vdd=3.6v, vi=vdd or gnd digital output low level (cf1, cf2, cf3, cf4, zx0, zx1, zx2, sdo) 0.4 v vdd=3.3v, i ol =8ma digital output low le vel (irq0, irq1, war- nout) 0.4 v vdd=3.3v, i ol =5ma digital output high level (cf1, cf2, cf3, cf4, zx0, zx1, zx2, sdo) vdd-0.4 v vdd=3.3v, i oh =-8ma, by separately digital output high level (irq0, irq1, war- nout) vdd-0.4 v vdd=3.3v, i oh =-5ma, by separately note1: guaranteed by design or char acterization, not production tested. note2: the maximum spi bit rate during current detector calibration is 900k bps. parameter min typ max unit test condition/ comments
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 74 6.2 metering/ measurement accuracy 6.2.1 metering accuracy metering accuracy or energy accuracy is calculated with relative error: where e mea is the energy measured by the meter, e real is the actual energy measured by a high accurate normative meter. table-16 metering accuracy for different energy within the dynamic range energy type energy pulse adc range when gain=1 metering accuracy note active energy (per phase and all-phase-sum) cf1 pf=1.0 120 v-720mv 0.1% pf=0.5l, 180 v-720mv pf=0.8c, 150 v-720mv reactive energy (per phase and all-phase-sum) cf2 sin =1.0 120 v-720mv 0.2% sin =0.5l, 180 v-720mv sin =0.8c, 150 v-720mv apparent energy (per phase and arithmetic all-phase- sum) cf2 600 v-720mv note 2 0.2% fundamental active energy (per phase and all-phase-sum) cf3 pf=1.0 120 v-720mv 0.2% pf=0.5l, 180 v-720mv pf=0.8c, 150 v-720mv harmonic active energy (per phase and all-phase-sum) cf4 pf=1.0 120 v-720mv 0.5% pf=0.5l, 180 v-720mv pf=0.8c, 150 v-720mv note 1: all the parameters in this ta ble is tested on atmel test platform. note 2: apparent energy is tested using ac tive energy with unity power factor since there?s no standard for apparent energy. si gnal below 600 v is not tested. % 100 ? = real real mea e e e
75 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 6.2.2 measurement accuracy the measurements are all calculated with fiducial error except for frequency. fiducial error is calculated as follows: where u mea means the measured data of one measurement parameter, and u real means the real/actual data of the parameter, u fv means the fiducial value of this measur ement parameter, which can be defined as table-17 . for the above mentioned parameters, the measur ement accuracy requirement is 0.5% maximum. for frequency, temperature: parameter accuracy frequency: 0.01hz temperature: 1 c accuracy of all orders of harmonics: 5% relative error table-17 measurement parameter range and format measurement fiducial value (fv) m90e32as defined format range comment voltage reference voltage un xxx.xx 0 ~ 655.35v unsi gned integer with unit of 0.01v current maximum current imax (4in is recom- mended) xx.xxx 0 ~ 65.535a unsigned in teger with unit of 0.001a voltage rms un xxx.xx 0 ~ 65 5.35v unsigned in teger with un it of 0.01v current rms note 1 ib/in xx.xxx 0 ~ 65.535a unsigned integer with unit of 0.001a frequency reference fre- quency 50 hz xx.xx 45.00~65.00 hz signed integer with unit/lsb of 0.01hz power factor 1.000 x.xxx -1.000 ~ +1.0 00 signed integer, lsb/unit = 0.001 phase angle note 2 180 xxx.x -180 ~ +180 signed integer, unit/lsb = 0.1 note 1: all registers are of 16-bit. for cases when the current or active/reactive/apparent power goes beyond the above range, it is su ggested to be handled by mcu in application. for example, register value can be calibrated to 1/2 of the actual value during calibratio n, then multiply 2 in application. note 2: phase angle is obtained when voltage/current crosses zero at the sampling frequency of 256khz. 100% * u u - u rror fiducial_e fv real mea =
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 76 6.3 interface timing 6.3.1 spi interface timing (slave mode) the spi interface timing is as shown in figure-22 and table-18 . figure-22 spi timing diagram table-18 spi timing specification symbol description min. typical max. unit t csh minimum cs high level time 2t note 1 +10 ns t css cs setup time 2t+10 ns t csd cs hold time 3t+10 ns t cld clock disable time 1t ns t cyc sclk cycle 7t+10 ns t clh clock high level time 5t+10 ns t cll clock low level time 2t+10 ns t dis data setup time 2t+10 ns t dih data hold time 1t+10 ns t dw minimum data width 3t+10 ns t pd output delay 2t+20 ns t df output disable time 2t+20 ns note: 1. t means system clock cycle. t=1/ f sys_clk cs sclk sdi sdo t csh t css high impedance high impedance t csd t clh t cll t dis t dih t pd t df valid input valid output t cld t dw t cyc
77 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 6.4 power on reset timing in most case, the power of m90e32as and mcu are both derived from 220v power lines. to make sure m90e32as is reset and can work properly, mcu must force m90e32as into id le mode firstly and then into normal mode. in this opera- tion, reset is held to high in idle mode and de-asserted by delay t1 after idle-normal transition. refer to figure-23 . figure-23 power on reset timing (m90e32as and mcu are powered on simultaneously) figure-24 power on reset timing in normal & partial measurement mode table-19 power on reset specification symbol description min typ max unit v h power on trigger voltage 2.5 2.7 v t 0 duration forced in idle mode after power on 1 ms t 1 delay time after power on or exit idle mode 5 16 40 ms pm[1:0] idle mode normal mode dvdd mcu startup internal p o r t 1 t 0 dvdd internal por t 1 v h
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 78 6.5 zero-crossing timing figure-25 zero-crossing ti ming diagram (per phase) table-20 zero-crossing specification symbol description min typ max unit t zx high level width 5 ms t d delay time 0.2 0.5 ms zx (positive zero-crossing) zx (negative zero-crossing) zx (all zero-crossing) t zx t d v
79 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 6.6 voltage sag a nd phase loss timing figure-26 voltage sag and phase loss timing diagram time voltage + threshold - threshold irq (if enabled) sag/phase loss condition found in configured period assert of voltage sag / phase loss configured period
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 80 6.7 absolute maximum rating parameter maximum limit relative voltage between avdd and agnd -0.3v~4.5v relative voltage between dvdd and dgnd -0.3v~4.5v analog input voltage (i1p, i1n, i2p, i2n, i3p, i3n, v1p, v1n, v2p, v2n, v3p, v3n) -0.6v~avdd digital input voltage -0.3v~dvdd -0.3v~5.5v, for 5v tolerance pins operating temperature range -50~120 c maximum junction temperature 150 c package type thermal resistance ja unit condition tqfp48 58.5 c/w no airflow
81 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 ordering information atmel ordering code package carrier temperature range atm90e32as-au-r tqfp48 tape&reel industry (-40 c to +85 c ) atm90e32as-au-y tqfp48 tray industry (-40 c to +85 c )
m90e32as [prelimin ary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 82 package dimensions
83 m90e32as [preliminary datasheet] atmel-46003a-se-m90e32as-datasheet_052014 revision history doc. rev. date comments 46003a 05/20/2014 initial document release in atmel.
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